Patent US5731723A successfully refreshed from Google Patents.
US5731723A
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Half symbol delay calibration for phase window centering
Assignee: Silicon Systems Inc
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Filing: 1995-12-11
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Granted: 1998-03-24
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Expires: 2015-12-11
Abstract
Abstract The present invention provides a method and apparatus for half symbol delay calibration for phase window centering. To perform calibration of phase window centering, a carefully designed input signal is applied to the data signal input of a phase detector and a corresponding gating signal is applied to each of two D flip-flops. A calibration circuit produces the gating signal to enable the D flip-flops and the complement of the gating signal to temporarily prevent disturbance of a charge pump. In the preferred embodiment of the present invention, the calibration circuit provides a divide-by-4 clock function. The carefully designed input signal used for calibration includes on-time pulses and time-shifted pulses. The on-time pulses have rising edges that rise with the rising edges of the VCO clock signal. The time-shifted pulses follow the on-time pulses by 2.5 clock cycles of the VCO clock signal. If the half symbol delay is optimized, the phase detector will be equally likely to produce a pump up or a pump down signal. If the time-shifted pulses occur early or late relative to the rising edges of the VCO clock signal, then there will be more pump up or more pump down signals respectively. This information is used to calibrate the half symbol delay.
Inventors
- 👤 Shin Chung Chen
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 15:53
CPC Classifications
H; H03; H03L; H03L7/00; H03L7/06; H03L7/08; H03L7/14; H03L7/081; H04; H04L; H04L7/00; H04L7/02; H04L7/033
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
194 words
A method for providing half symbol delay calibration comprising the steps of: apply an on-time pulse to a first input of a half symbol delay circuit to provide an initial synchronization to said half delay calibration; applying a time-shifted pulse, with respect to said on-time pulse, to a second input of said half symbol delay circuit; comparing timing of said time-shifted pulse relative to a VCO clock; producing a charge pump charging signal and a charge pump discharging signal, said charge pump charging signal and said charge pump discharging signal having active durations based on said timing of said time-shifted pulse relative to said VCO clock; performing a logical OR operation to produce a signal based on said charge pump charging signal and said charge pump discharging signal; producing a timing signal having a period equal to an integer multiple of a clock period of said VCO clock; producing a first output signal based on said charge pump charging signal and said timing signal; producing a second output signal based on said charge pump discharging signal and said timing signal; and providing said half symbol delay based on said first and second output signals.
Claim 2
Independent Claim
194 words
A method for providing half symbol delay calibration comprising the steps of: apply an on-time pulse to a first input of a half symbol delay circuit to provide an initial synchronization to said half delay calibration; applying a time-shifted pulse, with respect to said on-time pulse, to a second input of said half symbol delay circuit; comparing timing of said time-shifted pulse relative to a VCO clock; producing a charge pump charging signal and a charge pump discharging signal, said charge pump charging signal and said charge pump discharging signal having active durations based on said timing of said time-shifted pulse relative to said VCO clock; performing a logical OR operation to produce a signal based on said charge pump charging signal and said charge pump discharging signal; producing a timing signal having a period equal to an integer multiple of a clock period of said VCO clock; producing a first output signal based on said charge pump charging signal and said timing signal; producing a second output signal based on said charge pump discharging signal and said timing signal; and providing said half symbol delay based on said first and second output signals.
Claim 3
Dependent Claim
144 words
Apparatus for providing half symbol delay calibration comprising: a half symbol delay circuit for introducing a delay in a data pulse signal, said data pulse signal comprising a data pulse; a phase detector coupled to said half symbol delay circuit for detecting a phase of said data pulse to provide a first output signal and a second output signal; a calibration circuit coupled to said phase detector for calibrating said delay from said half symbol delay circuit to provide a calibration circuit output signal; a charge pump circuit coupled to said calibration circuit for receiving said first output signal, said second output signal, and said calibration circuit output signal and for providing a charge pump output signal; and a voltage controlled oscillator coupled to said charge pump circuit for receiving said charge pump output signal and for providing a voltage controlled oscillator output signal.
Claim 4
Dependent Claim
144 words
Apparatus for providing half symbol delay calibration comprising: a half symbol delay circuit for introducing a delay in a data pulse signal, said data pulse signal comprising a data pulse; a phase detector coupled to said half symbol delay circuit for detecting a phase of said data pulse to provide a first output signal and a second output signal; a calibration circuit coupled to said phase detector for calibrating said delay from said half symbol delay circuit to provide a calibration circuit output signal; a charge pump circuit coupled to said calibration circuit for receiving said first output signal, said second output signal, and said calibration circuit output signal and for providing a charge pump output signal; and a voltage controlled oscillator coupled to said charge pump circuit for receiving said charge pump output signal and for providing a voltage controlled oscillator output signal.
Claim 5
Dependent Claim
143 words
Apparatus for providing half symbol delay calibration comprising: a phase detector for detecting the phase of a data pulse to provide a first output signal and a second output signal; a first logic gate coupled to said phase detector for receiving said first output signal and said second output signal and for providing a third output signal; a first D flip-flop coupled to said first logic gate for receiving said third output signal and for providing a fourth output signal; a second D flip-flop coupled to said first D flip-flop for receiving said fourth output signal and for providing a fifth output signal; a third D flip-flop coupled to said first D flip-flop for receiving said fourth output signal and for providing a sixth output signal; and a half symbol delay calibration circuit for calibrating said apparatus based on said sixth output signal.
Claim 6
Dependent Claim
143 words
Apparatus for providing half symbol delay calibration comprising: a phase detector for detecting the phase of a data pulse to provide a first output signal and a second output signal; a first logic gate coupled to said phase detector for receiving said first output signal and said second output signal and for providing a third output signal; a first D flip-flop coupled to said first logic gate for receiving said third output signal and for providing a fourth output signal; a second D flip-flop coupled to said first D flip-flop for receiving said fourth output signal and for providing a fifth output signal; a third D flip-flop coupled to said first D flip-flop for receiving said fourth output signal and for providing a sixth output signal; and a half symbol delay calibration circuit for calibrating said apparatus based on said sixth output signal.
Claim 7
Dependent Claim
164 words
Apparatus for providing half symbol delay calibration comprising: a phase detector for detecting the phase of a data pulse to provide a first output signal and a second output signal; a first logic gate coupled to said phase detector for receiving said first output signal and said second output signal and for providing a third output signal; a first D flip-flop coupled to said first logic gate for receiving said third output signal and for providing a fourth output signal; a second D flip-flop coupled to said first D flip-flop for receiving said fourth output signal and for providing a fifth output signal; a third D flip-flop coupled to said first D flip-flop for receiving said fourth output signal and for providing a sixth output signal, wherein the apparatus further comprises a second logic gate coupled to said phase detector and to said second D flip-flop for receiving said first output signal and said fifth output signal and for providing a seventh output signal.
Claim 8
Dependent Claim
164 words
Apparatus for providing half symbol delay calibration comprising: a phase detector for detecting the phase of a data pulse to provide a first output signal and a second output signal; a first logic gate coupled to said phase detector for receiving said first output signal and said second output signal and for providing a third output signal; a first D flip-flop coupled to said first logic gate for receiving said third output signal and for providing a fourth output signal; a second D flip-flop coupled to said first D flip-flop for receiving said fourth output signal and for providing a fifth output signal; a third D flip-flop coupled to said first D flip-flop for receiving said fourth output signal and for providing a sixth output signal, wherein the apparatus further comprises a second logic gate coupled to said phase detector and to said second D flip-flop for receiving said first output signal and said fifth output signal and for providing a seventh output signal.
Claim 9
Dependent Claim
40 words
The apparatus of claim 4 further comprising: a third logic gate coupled to said phase detector and to said second D flip-flop for receiving said second output signal and said fifth output signal and for providing an eighth output signal.
Claim 10
Dependent Claim
39 words
The apparatus of claim 5 further comprising: a charge pump coupled to said second logic gate and said third logic gate for receiving said seventh output signal and said eighth output signal and for providing a ninth output signal.
Claim 11
Dependent Claim
29 words
The apparatus of claim 6 further comprising: a voltage controlled oscillator coupled to said charge pump for receiving said ninth output signal and for providing a tenth output signal.
Claim 12
Dependent Claim
154 words
Apparatus for providing half symbol delay calibration comprising: a phase detector for detecting the phase of a data pulse to provide a first output signal and a second output signal; a first logic gate coupled to said phase detector for receiving said first output signal and said second output signal and for providing a third output signal; a first D flip-flop coupled to said first logic gate for receiving said third output signal and for providing a fourth output signal; a second D flip-flop coupled to said first D flip-flop for receiving said fourth output signal and for providing a fifth output signal; and a third D flip-flop coupled to said first D flip-flop for receiving said fourth output signal and for providing a sixth output signal, wherein said second D flip-flop further provides a seventh output signal, said third D flip-flop coupled to said second flip flop for receiving said seventh output signal.
Claim 13
Dependent Claim
154 words
Apparatus for providing half symbol delay calibration comprising: a phase detector for detecting the phase of a data pulse to provide a first output signal and a second output signal; a first logic gate coupled to said phase detector for receiving said first output signal and said second output signal and for providing a third output signal; a first D flip-flop coupled to said first logic gate for receiving said third output signal and for providing a fourth output signal; a second D flip-flop coupled to said first D flip-flop for receiving said fourth output signal and for providing a fifth output signal; and a third D flip-flop coupled to said first D flip-flop for receiving said fourth output signal and for providing a sixth output signal, wherein said second D flip-flop further provides a seventh output signal, said third D flip-flop coupled to said second flip flop for receiving said seventh output signal.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-03-23 | 2001-09-22 | 2002-03-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-03-23 | 2005-09-22 | 2006-03-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-03-23 | 2009-09-22 | 2010-03-24 | $7700.00 | Window Closed / Lapsed |