Disk recording apparatus with adaptive window adjusting

Claim 2

A disk recording apparatus wherein a second read signal is produced from a first read signal read out from a disk shaped record medium, comprising: a data separator chip which includes: a signal processing meads which produces said second read signal by employing a window which has been formed based upon a clock pulse generated from said first read signal, window timing varying means for varying timing of said window relative to said first read signal, and memory means for holding control data which is used by said window timing varying means; a microprocessing chip for setting said control data to said memory means of said data separator chip for adjusting window timing of said window relative to said first read signal; and window error detecting means for judging whether an error has occurred in said second read signal produced by said signal processing means, wherein said microprocessor chip executes varying of said control data, calculating of first data from said control data at borders of said error and setting of said first data as said control data in memory means.

Claim 3

A disk recording apparatus according to claim 1, wherein said microprocessor chip automatically executes said varying, calculating and setting when the apparatus is not performing a read operation.

Claim 4

A disk recording apparatus according to claim 1, wherein said microprocessor chip calculates said first data by obtaining a maximum and a minimum delay amount through varying and dividing each of the maximum and minimum delay amount into an arbitrary ratio.

Claim 5

A disk recording apparatus according to claim 1, further comprising: a test signal generator for producing a test signal in place of said first read signal for detection in said window error detecting means.

Claim 6

A disk recording apparatus wherein a second read signal is produced from a first read signal read out from a disk shaped record medium, comprising: a disk separator which includes: phase synchronizing means, into which said first read signal is input, for generating a clock pulse in synchronism with said first read signal, synchronizing means, into which said first read signal and said clock pulse produced from said phase synchronizing means are input, for producing said second read signal by employing a window which has been formed based upon said clock pulse, window timing adjusting means for adjusting timing of said window relative to said first read signal based on control data, and memory means for holding control data which is used by said window timing adjusting means; a microprocessing chip for producing first data for adjusting timing of said window to minimize error-rate of said second read signal and setting said first data as said control data to said memory means; and window error detecting means for judging whether an error has occurred in said second read signal produced by said synchronizing means; wherein said microprocessing chip executes: setting of a plurality of second data for setting various timing of said window as said control data respectively in said memory means, getting of data from said window error detecting means which indicates whether an error has occurred or not in said second read signal in response to said second data respectively, calculating of first control data employing data from said window error detecting means and setting of said first data as said control data in memory means; and wherein said microprocessing chip calculates said first data by obtaining allowable maximum and minimum delay amount through setting of a plurality of second data and dividing the maximum and minimum delay amount into an arbitrary ratio.

Claim 7

A disk recording apparatus wherein a second read signal is produced from a first read signal read out from a disk shaped record medium, comprising: a disk separator which includes: phase synchronizing means, into which said first read signal is input, for generating a clock pulse in synchronism with said first read signal, synchronizing means, into which said first read signal and said clock pulse produced from said phase synchronizing means are input, for producing said second read signal by employing a window which has been formed based upon said clock pulse, window timing adjusting means for adjusting timing of said window relative to said first read signal based on control data, and memory means for holding control data which is used by said window timing adjusting means; a microprocessing chip for producing first data for adjusting timing of said window to minimize error-rate of said second read signal and setting said first data as said control data to said memory means; and window error detecting means for judging whether an error has occurred in said second read signal produced by said synchronizing means; wherein said microprocessing chip executes: setting of a plurality of second data for setting various timing of said window as said control data respectively in said memory means, getting of data from said window error detecting means which indicates whether an error has occurred or not in said second read signal in response to said second data respectively, calculating of first control data employing data from said window error detecting means and setting of said first data as said control data in memory means; and wherein said microprocessing chip calculates said first data by obtaining allowable maximum and minimum delay amount through setting of a plurality of second data and dividing the maximum and minimum delay amount into an arbitrary ratio.