US4894734A
Expired / Lapsed
US
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Method and apparatus for constant density recording
Assignee: Maxtor Corp
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Filing: 1987-05-15
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Granted: 1990-01-16
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Expires: 2007-05-15
Abstract
Abstract Method and apparatus for providing constant density recording is described. A single set of reconfigurable electronics is employed to control the write frequency for a plurality of frequency zones on a magnetic storage disk. The reconfigurable electronics include means for selectively switching a frequency response determining element within a common channel. Switching is controlled by a digital signal provided by a disk file control microprocessor, avoiding the necessity of mechanical linkages and/or changes in spindle rotation rate. The plurality of zones need not be of equal radius in width but the recording frequency within each zone is fixed throughout that zone. Zone selection is under the control of a disk file control microprocessor which produces a digital code to appropriately configure the electronics for the particular zone. Zone switching is done only when a seek across a zone boundary occurs so that no access time penalties result.
Inventors
- 👤 Al Fischler
- 👤 Ross Wilson
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 07:51
CPC Classifications
G; G11; G11B; G11B5/00; G11B5/012; G11B20/00; G11B20/10; G11B20/14; G11B20/1403; G11B20/12; G11B20/1217; G11B20/1258; G11B2020/10916
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
335 words
A circuit for reading and writing data with a read/write head at a plurality of constant frequency zones on a data storage disk comprising: identifying means coupled to said read/write head for detecting a first identification signal identifying a track of said storage disk and assigning one of a plurality of zone select codes to said track, each zone select code corresponding to one of said constant frequency zones; clock signal generating means coupled to said zone select code and to a first clock signal having a first frequency, said clock signal generating means outputting a second clock signal having a second frequency dependent on said zone select code such that a different frequency is produced for each said constant frequency zones; data separating means coupled to said second clock signal for defining data recovery windows for separating data during a read operation, said data separating means outputting a data clock for controlling the frequency of a write operation; a read channel coupled to said read/write head and to said data separating means for converting analog data signals into digital data signals; encoding means coupled to said data separating means for writing data at a frequency corresponding to said second frequency; decoding means coupled to said data separating means for reading data from said constant frequency zones of said data storage disk at said second frequency; said zone select code comprising a digital code having a numerical value dependent on said constant frequency zone; said clock signal generating means comprising means for multiplying said first clock signal by a weighting factor corresponding to said numerical value of said zone select code; said data separating means comprising a variable frequency oscillator (VFO) and said data separating means may be selectively coupled to said clock signal generating means and said read channel; said data separating means further including a digital to analog converter coupled to said zone select code, said digital to analog converter having an output defining a center frequency of a voltage controlled oscillator (VCO).
Claim 2
Dependent Claim
335 words
A circuit for reading and writing data with a read/write head at a plurality of constant frequency zones on a data storage disk comprising: identifying means coupled to said read/write head for detecting a first identification signal identifying a track of said storage disk and assigning one of a plurality of zone select codes to said track, each zone select code corresponding to one of said constant frequency zones; clock signal generating means coupled to said zone select code and to a first clock signal having a first frequency, said clock signal generating means outputting a second clock signal having a second frequency dependent on said zone select code such that a different frequency is produced for each said constant frequency zones; data separating means coupled to said second clock signal for defining data recovery windows for separating data during a read operation, said data separating means outputting a data clock for controlling the frequency of a write operation; a read channel coupled to said read/write head and to said data separating means for converting analog data signals into digital data signals; encoding means coupled to said data separating means for writing data at a frequency corresponding to said second frequency; decoding means coupled to said data separating means for reading data from said constant frequency zones of said data storage disk at said second frequency; said zone select code comprising a digital code having a numerical value dependent on said constant frequency zone; said clock signal generating means comprising means for multiplying said first clock signal by a weighting factor corresponding to said numerical value of said zone select code; said data separating means comprising a variable frequency oscillator (VFO) and said data separating means may be selectively coupled to said clock signal generating means and said read channel; said data separating means further including a digital to analog converter coupled to said zone select code, said digital to analog converter having an output defining a center frequency of a voltage controlled oscillator (VCO).
Claim 3
Dependent Claim
22 words
The circuit of claim 1 wherein said constant frequency zones are such that all of said zones have an equal data density.
Claim 4
Dependent Claim
17 words
The circuit of claim 2 wherein said plurality of constant frequency zones comprises 8 constant frequency zones.
Claim 5
Dependent Claim
331 words
A circuit having a single channel for reading and writing data with a single read/write head at a plurality of constant frequency zones on a data storage disk comprising: identifying means coupled to said read/write head for detecting a first identification signal identifying a track of said storage disk and assigning one of a plurality of zone select codes to said track, each zone select code corresponding to one of said constant frequency zones; clock signal generating means coupled to said zone select code and to a first clock signal having a first frequency, said clock signal generating means outputting a second clock signal having a second frequency dependent on said zone select code such that a different frequency is produced for each of said constant frequency zones; said clock signal generating means comprising a frequency synthesizer; data separating means coupled to said second clock signal for defining data recovery windows for separating data during a read operation, said data separating means outputting a data clock for controlling the frequency of a write operation, said data separating means comprising a variable frequency oscillator (FFO); a read channel coupled to said read/write head and to said data separating means for converting analog data signals into digital data signals; encoding means coupled to said data separating means for writing data at a frequency corresponding to said frequency; decoding means coupled to said data separating mean for reading data from said constant frequency zones of said data storage at said second frequency; coarse frequency control means included in said VFO coupled to said zone select code and a fine frequency control means coupled to said read channel and said zone select code; said fine frequency control means comprising a phase/frequency loop phase detector; said coarse frequency control means comprising a digital-to-analog converter coupled to a voltage controlled oscillator (VCO); said VFO further including an anticipator coupled to said read channel to provide a delay of approximately one half bit-cell in length in read data.
Claim 6
Dependent Claim
331 words
A circuit having a single channel for reading and writing data with a single read/write head at a plurality of constant frequency zones on a data storage disk comprising: identifying means coupled to said read/write head for detecting a first identification signal identifying a track of said storage disk and assigning one of a plurality of zone select codes to said track, each zone select code corresponding to one of said constant frequency zones; clock signal generating means coupled to said zone select code and to a first clock signal having a first frequency, said clock signal generating means outputting a second clock signal having a second frequency dependent on said zone select code such that a different frequency is produced for each of said constant frequency zones; said clock signal generating means comprising a frequency synthesizer; data separating means coupled to said second clock signal for defining data recovery windows for separating data during a read operation, said data separating means outputting a data clock for controlling the frequency of a write operation, said data separating means comprising a variable frequency oscillator (FFO); a read channel coupled to said read/write head and to said data separating means for converting analog data signals into digital data signals; encoding means coupled to said data separating means for writing data at a frequency corresponding to said frequency; decoding means coupled to said data separating mean for reading data from said constant frequency zones of said data storage at said second frequency; coarse frequency control means included in said VFO coupled to said zone select code and a fine frequency control means coupled to said read channel and said zone select code; said fine frequency control means comprising a phase/frequency loop phase detector; said coarse frequency control means comprising a digital-to-analog converter coupled to a voltage controlled oscillator (VCO); said VFO further including an anticipator coupled to said read channel to provide a delay of approximately one half bit-cell in length in read data.
Claim 7
Dependent Claim
306 words
A circuit having a single channel for reading and writing data with a single read/write head at a plurality of constant frequency zones on a data storage disk comprising: identifying means coupled to said read/write head for detecting a firs identification signal identifying a track of said storage disk and assigning plurality of zone select codes to said track, each zone select code corresponding to one of said constant frequency zones; clock signal generating means coupled to said zone select code and to clock signal having a first frequency, said clock signal generating means outputting a second clock signal and a delay clock signal each having a frequency dependent on said zone select code such that a different frequency is produced for each of said constant frequency zones; data separating means coupled to said second clock signal and said delay clock signal for defining data recovery windows for separating data during a read operation, said data separating means outputting a data clock for controlling the frequency of a write operation; a read channel coupled to said read/write head and to said data separating means for converting analog data signals into digital data signals; encoding means coupled to said data separating means for writing data at a frequency corresponding to said frequency; decoding means coupled to said data separating means for reading data from said constant frequency zones of said data storage disk at said second frequency; said clock signal generating means comprising a frequency synthesizing means coupled to said first clock signal and providing a first output signal, a dividing means coupled to said zone select code and providing a second output signal, first and second delay lines coupled to said first output signal and providing third and fourth output signals respectively, said fourth output signal coupled in a feedback loop to said second delay line.
Claim 8
Dependent Claim
306 words
A circuit having a single channel for reading and writing data with a single read/write head at a plurality of constant frequency zones on a data storage disk comprising: identifying means coupled to said read/write head for detecting a firs identification signal identifying a track of said storage disk and assigning plurality of zone select codes to said track, each zone select code corresponding to one of said constant frequency zones; clock signal generating means coupled to said zone select code and to clock signal having a first frequency, said clock signal generating means outputting a second clock signal and a delay clock signal each having a frequency dependent on said zone select code such that a different frequency is produced for each of said constant frequency zones; data separating means coupled to said second clock signal and said delay clock signal for defining data recovery windows for separating data during a read operation, said data separating means outputting a data clock for controlling the frequency of a write operation; a read channel coupled to said read/write head and to said data separating means for converting analog data signals into digital data signals; encoding means coupled to said data separating means for writing data at a frequency corresponding to said frequency; decoding means coupled to said data separating means for reading data from said constant frequency zones of said data storage disk at said second frequency; said clock signal generating means comprising a frequency synthesizing means coupled to said first clock signal and providing a first output signal, a dividing means coupled to said zone select code and providing a second output signal, first and second delay lines coupled to said first output signal and providing third and fourth output signals respectively, said fourth output signal coupled in a feedback loop to said second delay line.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-01-15 | 1993-07-17 | 1994-01-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-01-15 | 1997-07-17 | 1998-01-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-01-15 | 2001-07-17 | 2002-01-16 | $7700.00 | Window Closed / Lapsed |