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US5731234A
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Process for global planarization of memory and globally planarized memory
Assignee: United Microelectronics Corp
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Filing: 1996-06-25
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Granted: 1998-03-24
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Expires: 2016-06-25
Abstract
Abstract A process for the global planarization of a memory circuit and globally planarized memory. The process includes defining a memory cell circuit area and a peripheral circuit area on a silicon substrate. A memory cell MOS transistor is formed in the memory cell circuit area and at least two peripheral circuit MOS transistors are formed in the peripheral circuit area. A memory cell electronic component is then formed in the memory cell circuit area and in the peripheral circuit area from a plurality of thin film layers. The thin film layers are defined in the peripheral circuit area such that an open circuit is formed between the thin film layers and the peripheral circuit MOS transistors. A planarized insulating layer is then formed on top of the silicon substrate.
Inventors
- 👤 Anchor Chen
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 03:29
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/01
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
202 words
A method of manufacturing globally planarized memory, wherein the memory comprises more than one memory cell, and each memory cell comprises at least one MOS transistor and at least one other electronic component, comprising: (a) defining a memory cell circuit area and a peripheral circuit area on a silicon substrate; (b) forming a memory cell MOS transistor in the memory cell circuit area and forming more than one peripheral circuit MOS transistor in the peripheral circuit area; (c) forming a plural number of thin film layers in the memory cell circuit area and in the peripheral circuit area; (d) defining the plural number of thin film layers in the memory cell circuit area so as to form a memory cell electronic component in the memory cell circuit area, and further defining the thin film layers in the peripheral circuit area such that an open circuit is formed between the peripheral circuit MOS transistors while retaining each of the plural number of thin film layers in the peripheral circuit area; and (e) forming a planarized insulating layer on top of the silicon substrate over the plural number of thin film layers, in both the memory cell circuit area and the peripheral circuit area.
Claim 2
Independent Claim
202 words
A method of manufacturing globally planarized memory, wherein the memory comprises more than one memory cell, and each memory cell comprises at least one MOS transistor and at least one other electronic component, comprising: (a) defining a memory cell circuit area and a peripheral circuit area on a silicon substrate; (b) forming a memory cell MOS transistor in the memory cell circuit area and forming more than one peripheral circuit MOS transistor in the peripheral circuit area; (c) forming a plural number of thin film layers in the memory cell circuit area and in the peripheral circuit area; (d) defining the plural number of thin film layers in the memory cell circuit area so as to form a memory cell electronic component in the memory cell circuit area, and further defining the thin film layers in the peripheral circuit area such that an open circuit is formed between the peripheral circuit MOS transistors while retaining each of the plural number of thin film layers in the peripheral circuit area; and (e) forming a planarized insulating layer on top of the silicon substrate over the plural number of thin film layers, in both the memory cell circuit area and the peripheral circuit area.
Claim 3
Dependent Claim
14 words
A method according to claim 1, wherein the memory is dynamic random access memory.
Claim 4
Dependent Claim
13 words
A method according to claim 2, wherein the electronic component is a capacitor.
Claim 5
Dependent Claim
14 words
A method according to claim 1, wherein the memory is static random access memory.
Claim 6
Dependent Claim
14 words
A method according to claim 4, wherein the electronic component is a load resistor.
Claim 7
Dependent Claim
14 words
A method according to claim 1, wherein the planarized insulating layer is borophosphosilicate glass.
Claim 8
Dependent Claim
19 words
A method according to claim 1, wherein the plural number of thin film layers includes three thin film layers.
Claim 9
Dependent Claim
32 words
A method according to claim 7, wherein the three thin film layers includes a first polysilicon layer, a dielectric layer and a second polysilicon layer, and the electronic component is a capacitor.
Claim 10
Dependent Claim
55 words
A method according to claim 1, further comprising: (f) forming a contact window in the peripheral circuit area to expose a source/drain terminal; (g) filling the contact window with a conducting material; and (h) depositing simultaneously a metallic layer in the memory cell circuit area and the peripheral circuit area and forming conducting wires therefrom.
Claim 11
Dependent Claim
21 words
A method according to claim 1, wherein the forming a planarized insulating layer comprises forming the planarized insulating layer by CVD.
References Cited (Backward Citations)
US5486712A
Cited
US5374579A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-03-23 | 2001-09-22 | 2002-03-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-03-23 | 2005-09-22 | 2006-03-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-03-23 | 2009-09-22 | 2010-03-24 | $7700.00 | Window Closed / Lapsed |