DRAM having peripheral circuitry in which source-drain interconnection contact of a MOS transistor is made small by utilizing a pad layer and manufacturing method thereof

Claim 2

A DRAM including a memory cell region having a plurality of memory cells each formed of at least one MOS transistor and one capacitor, and a peripheral circuit for writing/reading prescribed memory information to and from the memory cell region, on a main surface of a semiconductor substrate, said DRAM comprising: a MOS transistor for each memory cell including a pair of first impurity regions formed in said semiconductor substrate and a first gate electrode formed on the semiconductor substrate between said pair of first impurity regions; a MOS transistor for the peripheral circuit including a pair of second impurity regions formed in said semiconductor substrate and a second gate electrode formed on said semiconductor substrate between said pair of second impurity regions; a first conductive layer connected to one of said first impurity regions of said MOS transistor for the memory cell; a second conductive layer connected to the other one of said first impurity regions of said MOS transistor for the memory cell, to form a lower electrode of said capacitor; a third conductive layer connected to one of said second impurity regions of said MOS transistor for the peripheral circuit and extending above at least a portion of said second gate electrode of said MOS transistor of the peripheral circuit; and a fourth conductive layer connected to another one of said second impurity regions of said MOS transistor for the peripheral circuit, and extending above at least a portion of said second gate electrode of said MOS transistor for the peripheral circuit and over at least a portion of said third conductive layer.

Claim 3

A DRAM according to claim 1, wherein a portion of said fourth conductive layer overlaps an upper portion of said third conductive layer, with an insulating layer interposed therebetween.

Claim 4

A DRAM according to claim 1, further comprising: an interlayer insulating layer having a relatively flat upper surface formed on both said peripheral circuit and said memory cell region.

Claim 5

A DRAM according to claim 1, wherein said peripheral circuit comprises a plurality of MOS transistors, each of said plurality of MOS transistors including a pair of impurity regions formed in said semiconductor substrate and said third conductive layer and said fourth conductive layer are each connected to a respective one of said pair of impurity regions each of said plurality of MOS transistors.

Claim 6

A DRAM according to claim 1, wherein said first conductive layer and said third conductive layer are formed of the same material selected from the group consisting of polycrystalline silicon, high melting point metal, and a combination of polycrystalline silicon and high melting point metal silicide; and said second conductive layer and said fourth conductive layer are formed of the same material selected from the group consisting of polycrystalline silicon, high melting point metal, and a combination of polycrystalline silicon and high melting point metal silicide.

Claim 7

A DRAM including a memory cell region having a plurality of memory cells each formed on one MOS transistor and one capacitor, and a peripheral circuit for writing/reading prescribed memory information to and from the memory cell region, on a main surface of a semiconductor substrate, comprising: a MOS transistor for each memory cell including a pair of first impurity regions formed in said semiconductor substrate and a first gate electrode formed on the semiconductor substrate between said pair of first impurity regions; a MOS transistor for the peripheral circuit including a pair of second impurity regions formed in said semiconductor substrate and a second gate electrode formed on said semiconductor substrate between said pair of second impurity regions; a first conductive layer connected to one of said first impurity regions of said MOS transistor for the memory cell; a second conductive layer separate and distinct from said first conductive layer connected to the other one of said first impurity regions of said MOS transistor for the memory cell, to form a lower electrode of said capacitor;. a third conductive layer connected to one of said second impurity regions of said MOS transistor for the peripheral circuit; and a fourth conductive layer separate and distinct from said first conductive layer connected to the other one of said second impurity regions of said MOS transistor for the peripheral circuit, wherein said second conductive layer overlaps an upper surface of said first conductive layer, and wherein a portion of said fourth conductive layer overlaps a portion of said third conductive layer, with an insulating layer interposed between said third and fourth conductive layers.

Claim 8

A DRAM including a memory cell region having a plurality of memory cells each formed on one MOS transistor and one capacitor, and a peripheral circuit for writing/reading prescribed memory information to and from the memory cell region, on a main surface of a semiconductor substrate, comprising: a MOS transistor for each memory cell including a pair of first impurity regions formed in said semiconductor substrate and a first gate electrode formed on the semiconductor substrate between said pair of first impurity regions; a MOS transistor for the peripheral circuit including a pair of second impurity regions formed in said semiconductor substrate and a second gate electrode formed on said semiconductor substrate between said pair of second impurity regions; a first conductive layer connected to one of said first impurity regions of said MOS transistor for the memory cell; a second conductive layer separate and distinct from said first conductive layer connected to the other one of said first impurity regions of said MOS transistor for the memory cell, to form a lower electrode of said capacitor;. a third conductive layer connected to one of said second impurity regions of said MOS transistor for the peripheral circuit; and a fourth conductive layer separate and distinct from said first conductive layer connected to the other one of said second impurity regions of said MOS transistor for the peripheral circuit, wherein said second conductive layer overlaps an upper surface of said first conductive layer, and wherein a portion of said fourth conductive layer overlaps a portion of said third conductive layer, with an insulating layer interposed between said third and fourth conductive layers.

Claim 9

A DRAM according to claim 6, further comprising: an interlayer insulating layer having a relatively flat upper surface formed on both said peripheral circuit and said memory cell region.

Claim 10

A DRAM according to claim 6, wherein said peripheral circuit comprises a plurality of MOS transistors, each of said plurality of MOS transistors including a pair of impurity regions formed in said semiconductor substrate and said third conductive layer and said fourth conductive layer are each connected to a respective one of said pair of impurity regions of each of said plurality of MOS transistors.

Claim 11

A DRAM according to claim 6, wherein said first conductive layer and said third conductive layer are formed of the same material selected from the group consisting of polycrystalline silicon, high melting point metal, and a combination of polycrystalline silicon and high melting point metal silicide; and said second conductive layer and said fourth conductive layer are formed of the same material selected from the group consisting of polycrystalline silicon, high melting point metal, and a combination of polycrystalline silicon and high melting point metal silicide.

Claim 12

A DRAM according to claim 1, wherein said peripheral circuit comprises a plurality of MOS transistors, including PMOS transistors and NMOS transistors, each of said plurality of MOS transistors including a pair of impurity regions formed in said semiconductor substrate and said third conductive layer and said fourth conductive layer are each connected to a respective one of said pair of impurity regions of each of said plurality of MOS transistors.

Claim 13

In a DRAM including a memory cell region having a plurality of memory cells each formed of at least one MOS transistor and one capacitor, a peripheral circuit for writing/reading prescribed memory information to and from the memory cell region, on a main surface of a semiconductor substrate, said peripheral circuit comprising: a MOS transistor for the peripheral circuit including a pair of impurity regions formed in said semiconductor substrate and a gate electrode formed on said semiconductor substrate between said pair of impurity regions; a first conductive layer connected to one of said impurity regions of said MOS transistor for the peripheral circuit and extending above at least a portion of said gate electrode of said MOS transistor of the peripheral circuit; and a second conductive layer connected to another one of said impurity regions of said MOS transistor for the peripheral circuit, and extending above at least a portion of said gate electrode of said MOS transistor for the peripheral circuit and over at least a portion of said first conductive layer.

Claim 14

In a DRAM including a memory cell region having a plurality of memory cells each formed of at least one MOS transistor and one capacitor, a peripheral circuit for writing/reading prescribed memory information to and from the memory cell region, on a main surface of a semiconductor substrate, said peripheral circuit comprising: a MOS transistor for the peripheral circuit including a pair of impurity regions formed in said semiconductor substrate and a gate electrode formed on said semiconductor substrate between said pair of impurity regions; a first conductive layer connected to one of said impurity regions of said MOS transistor for the peripheral circuit and extending above at least a portion of said gate electrode of said MOS transistor of the peripheral circuit; and a second conductive layer connected to another one of said impurity regions of said MOS transistor for the peripheral circuit, and extending above at least a portion of said gate electrode of said MOS transistor for the peripheral circuit and over at least a portion of said first conductive layer.

Claim 15

The DRAM of claim 11, further comprising an interlayer insulating layer having a relatively flat upper surface formed on both said peripheral circuit and said memory cell region.

Claim 16

The DRAM of claim 11, wherein a portion of said second conductive layer is overlapped with an upper portion of said first conductive layer, with an insulating layer posed therebetween.

Claim 17

The DRAM according to claim 11, wherein said peripheral circuit comprises a plurality of MOS transistors, each of said plurality of MOS transistors including a pair of impurity regions formed in said semiconductor substrate and said first conductive layer and said second conductive layer are each connected to a respective one of said pair of impurity regions each of said plurality of MOS transistors.

Claim 18

The DRAM according to claim 11, wherein said first conductive layer is formed of a material selected from the group consisting of polycrystalline silicon, high melting point metal, and a combination of polycrystalline silicon and high melting point metal silicide; and said second conductive layer is formed of a material selected from the group consisting of polycrystalline silicon, high melting point metal, and a combination of polycrystalline silicon and high melting point metal silicide.