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US5728623A
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Method of bonding a III-V group compound semiconductor layer on a silicon substrate
Assignee: NEC Corp
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Filing: 1995-03-16
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Granted: 1998-03-17
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Expires: 2015-03-16
Abstract
Abstract Prior to a heat treatment for bonding a III-V group compound semiconductor layer on a silicon substrate, a thermal stress relaxation layer is provided between the silicon layer and the III-V group compound semiconductor layer thermal stress relaxation layer, having a thermal expansion coefficient equal or near to the thermal expansion coefficient of the III-V group compound semiconductor layer and having a rigidity coefficient being sufficiently large to suppress generation of any crystal defects in the III-V group compound semiconductor layer due to a thermal stress generated in the heat treatment and subsequent cooling stage by the difference in the thermal expansion coefficient between the III-V group compound semiconductor layer and the silicon layer.
Inventors
- 👤 Kazuo Mori
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 06:03
CPC Classifications
H; H10; H10P; H10P10/00; H10P10/12; H10P10/128; Y; Y10; Y10S; Y10S148/00; Y10S148/012; Y10S438/00; Y10S438/933
Claims Analysis
Total Claims: 31
Claim 1
Independent Claim
190 words
A method for bonding a III-V group compound semiconductor layer to a silicon layer, said III-V group compound semiconductor layer having a different thermal expansion coefficient from a thermal expansion coefficient of said silicon layer and having a different rigidity coefficient from a rigidity coefficient of said silicon layer, said method comprising the steps of: preparing an intermediate layer sandwiched between said silicon layer and said III-V group compound semiconductor layer; and subjecting said intermediate, silicon and III-V group compound semiconductor layers to a heat treatment at a temperature not less than 450° C.; wherein said intermediate layer comprises a thermal stress relaxation layer having a thermal expansion coefficient equal or near to the thermal expansion coefficient of said III-V group compound semiconductor layer and having a rigidity coefficient substantially greater than a rigidity coefficient of said III-V group compound semiconductor layer, thereby to suppress generation of any crystal defects in said III-V group compound semiconductor layer due to a thermal stress generated in said heat treatment and subsequent cooling stage by the difference in the thermal expansion coefficient between said III-V group compound semiconductor layer and said silicon layer.
Claim 2
Independent Claim
190 words
A method for bonding a III-V group compound semiconductor layer to a silicon layer, said III-V group compound semiconductor layer having a different thermal expansion coefficient from a thermal expansion coefficient of said silicon layer and having a different rigidity coefficient from a rigidity coefficient of said silicon layer, said method comprising the steps of: preparing an intermediate layer sandwiched between said silicon layer and said III-V group compound semiconductor layer; and subjecting said intermediate, silicon and III-V group compound semiconductor layers to a heat treatment at a temperature not less than 450° C.; wherein said intermediate layer comprises a thermal stress relaxation layer having a thermal expansion coefficient equal or near to the thermal expansion coefficient of said III-V group compound semiconductor layer and having a rigidity coefficient substantially greater than a rigidity coefficient of said III-V group compound semiconductor layer, thereby to suppress generation of any crystal defects in said III-V group compound semiconductor layer due to a thermal stress generated in said heat treatment and subsequent cooling stage by the difference in the thermal expansion coefficient between said III-V group compound semiconductor layer and said silicon layer.
Claim 3
Dependent Claim
27 words
The method as claimed in claim 1, wherein said thermal stress relaxation layer comprises a semiconductor material including at least any one of Ge, Ga and Al.
Claim 4
Dependent Claim
19 words
The method as claimed in claim 2, wherein said thermal stress relaxation layer includes at least a Ge layer.
Claim 5
Dependent Claim
20 words
The method as claimed in claim 2, wherein said thermal stress relaxation layer includes at least an SiGe amorphous layer.
Claim 6
Dependent Claim
20 words
The method as claimed in claim 2, wherein said thermal stress relaxation layer includes at least an Si/Ge superlattice layer.
Claim 7
Dependent Claim
19 words
The method as claimed in claim 2, wherein said thermal stress relaxation layer includes at least an AlP layer.
Claim 8
Dependent Claim
19 words
The method as claimed in claim 2, wherein said thermal stress relaxation layer includes at least a GaP layer.
Claim 9
Dependent Claim
19 words
The method as claimed in claim 2, wherein said thermal stress relaxation layer includes at least an AlAs layer.
Claim 10
Dependent Claim
19 words
The method are claimed in claim 2, wherein said thermal stress relaxation layer includes at least a GaAs layer.
Claim 11
Dependent Claim
38 words
The method as claimed in claim 2, wherein said thermal stress relaxation layer includes at least a layer of amorphous semiconductors including at least two compound semiconductors selected from the group consisting of AlP, GaP, AlAs and GaAs.
Claim 12
Dependent Claim
42 words
The method as claimed in claim 2, wherein said thermal stress relaxation layer includes at least a superlattice layer of two kinds of compound semiconductor layers, said two compound semiconductors being selected from the group consisting of AlP, GaP, AlAS and GaAs.
Claim 13
Dependent Claim
94 words
The method as claimed in claim 1, wherein said first preparation step further includes the step of forming a strained semiconductor layer between said intermediate layer and said III-V group compound semiconductor layer, said strained semiconductor layer being capable of preventing a threading dislocation extending through said strained layer into said III-V group compound semiconductor layer, said threading dislocation being caused by a thermal stress generated in said heat treatment and subsequent cooling stage due to the difference in the thermal expansion coefficient between said III-V group compound semiconductor layer and said silicon layer.
Claim 14
Dependent Claim
69 words
The method as claimed in claim 12, wherein said strained semiconductor layer includes at least a semiconductor layer having a rigidity coefficient being sufficiently small to permit generation of crystal defects in said strained semiconductor layer by a thermal stress generated in said heat treatment and subsequent cooling stage due to the difference in the thermal expansion coefficient between said III-V group compound semiconductor layer and said silicon layer.
Claim 15
Dependent Claim
25 words
The method as claimed in claim 13, wherein said strained semiconductor layer comprises a semiconductor material including at least any one of In and Sb.
Claim 16
Dependent Claim
28 words
The method as claimed in claim 12, wherein said strained semiconductor layer comprises a lamination of at least two semiconductor layers having different lattice constants from each other.
Claim 17
Dependent Claim
27 words
The method as claimed in claim 12, wherein said strained semiconductor layer comprises a lamination of at least two semiconductor layers having different planes from each other.
Claim 18
Dependent Claim
31 words
The method as claimed in claim 12, wherein said strained semiconductor layer comprises a lamination of at least two semiconductor layers having different crystal axes in tilted angle from each other.
Claim 19
Dependent Claim
31 words
The method as claimed in claim 12, wherein said strained semiconductor layer comprises a lamination of at least two semiconductor layers having different crystal axes in rotation direction from each other.
Claim 20
Dependent Claim
17 words
The method as claimed in claim 12, wherein said strained semiconductor layer comprises strained semiconductor super-lattice layers.
Claim 21
Dependent Claim
17 words
The method as claimed in claim 19, wherein said strained semiconductor super-lattice layers comprises InAlAs/InGaAs super-lattice layers.
Claim 22
Dependent Claim
117 words
The method as claimed in claim 1, wherein said first preparation step further includes the step of forming an amorphous semiconductor layer between said intermediate layer and said III-V group compound semiconductor layer, said amorphous semiconductor layer being capable of preventing a threading dislocation to extend through said strained layer into said III-V group compound semiconductor layer, said threading dislocation being caused by a thermal stress generated in said heat treatment and subsequent cooling stage due to the difference in the thermal expansion coefficient between said III-V group compound semiconductor layer and said silicon layer, and said amorphous semiconductor layer comprising an amorphous semiconductor being kept in amorphous state even after said heat treatment was carried out.
Claim 23
Dependent Claim
116 words
The method as claimed in claim 1, wherein said first preparation step further includes the step of forming an insulation layer in amorphous between said intermediate layer and said III-V group compound semiconductor layer, said insulation layer being capable of preventing a threading dislocation to extend through said strained layer into said III-V group compound semiconductor layer, said threading dislocation being caused by a thermal stress generated in said heat treatment and subsequent cooling stage due to the difference in the thermal expansion coefficient between said III-V group compound semiconductor layer and said silicon layer, and said insulation layer comprising an insulation material being kept in amorphous state even after said heat treatment was carried out.
Claim 24
Dependent Claim
16 words
The method as claimed in claim 22, wherein said insulation layer comprises a SiO 2 layer.
Claim 25
Dependent Claim
22 words
The method as claimed in claim 1, wherein said III-V group semiconductor layer includes at least any one of In and Sb.
Claim 26
Dependent Claim
60 words
The method as claimed in claim 1, wherein said first preparation step further includes the step of forming at least a semiconductor contact layer between said III-V group compound semiconductor layer and said thermal stress relaxation layer, said semiconductor contact layer having a rigidity coefficient being sufficiently small for facilitating atomic rearrangements in said contact layer by said heat treatment.
Claim 27
Dependent Claim
21 words
The method as claimed in claim 25, wherein said semiconductor contact layer includes at least any one of In and Sb.
Claim 28
Dependent Claim
48 words
The method as claimed in claim 1, wherein said first preparation step further includes the step of forming at least an insulation contact layer between said III-V group compound semiconductor layer and said thermal stress relaxation layer to permit a low temperature bonding with a static voltage application.
Claim 29
Dependent Claim
65 words
The method as claimed in claim 1, wherein said first preparation step further comprises the steps of: forming said thermal stress relaxation layer on said silicon layer; forming said III-V group compound semiconductor layer on a supporting substrate made of the same compound semiconductors as said III-V group compound semiconductor layer; and contacting said thermal stress relaxation layer with said III-V group compound semiconductor layer.
Claim 30
Dependent Claim
65 words
The method as claimed in claim 1, wherein said first preparation step comprises the steps of: forming said III-V group compound semiconductor layer on a supporting substrate made of the same compound semiconductors as said III-V group compound semiconductor layer; and forming said thermal stress relaxation layer on said III-V group compound semiconductor layer; and contacting said thermal stress relaxation layer with said silicon layer.
Claim 31
Dependent Claim
25 words
The method as claimed in claim 1, wherein said preparing step comprises forming said intermediate layer to a thickness of at least about 1 micron.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-03-16 | 2001-09-15 | 2002-03-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-03-16 | 2005-09-15 | 2006-03-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-03-16 | 2009-09-15 | 2010-03-17 | $7700.00 | Window Closed / Lapsed |