US5346848A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of bonding silicon and III-V semiconductor materials
Assignee: Motorola Solutions Inc
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Filing: 1993-06-01
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Granted: 1994-09-13
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Expires: 2013-06-01
Abstract
Abstract A silicon wafer and a III-V semiconductor wafer are bonded together through a bonding interlayer which is deposited on the III-V semiconductor wafer. By forming the bonding interlayer on the III-V semiconductor wafer, rather than the silicon wafer, the bonding process is facilitated, creating a sufficiently strong bond to carry out further processing. The III-V semiconductor wafer is thinned to relieve stress after the bonding procedure. The bonded wafers may be subjected to a second bonding procedure to increase the bond strength. The bonded wafers can then be subjected to high temperature processing used in semiconductor device fabrication.
Inventors
- 👤 Melissa E. Grupen-Shemansky
- 👤 Bertrand F. Cambou
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 07:39
CPC Classifications
H; H10; H10P; H10P90/00; H10P90/19; H10P90/1904; H10P90/1906; H10P90/1914; Y; Y10; Y10S; Y10S148/00; Y10S148/012; Y10S148/135
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
152 words
A method of bonding a silicon wafer and a III-V semiconductor wafer, comprising the steps of: providing a silicon wafer having a first and a second major surface; providing a III-V semiconductor wafer having a first and a second major surface; forming a bonding interlayer on the first major surface of the III-V semiconductor wafer; bonding the silicon wafer and the III-V semiconductor wafer together by using a first thermal or a thermo-anodic bonding process, such that the bonding interlayer is positioned between the III-V semiconductor wafer and the first major surface of the silicon wafer; removing a portion of the III-V semiconductor wafer from the second major surface of the III-V semiconductor wafer; and subjecting the III-V semiconductor wafer and the silicon wafer to a second thermal or thermo-anodic bonding process at a temperature less than approximately 200° C. after the step of removing a portion of the III-V semiconductor wafer.
Claim 2
Independent Claim
152 words
A method of bonding a silicon wafer and a III-V semiconductor wafer, comprising the steps of: providing a silicon wafer having a first and a second major surface; providing a III-V semiconductor wafer having a first and a second major surface; forming a bonding interlayer on the first major surface of the III-V semiconductor wafer; bonding the silicon wafer and the III-V semiconductor wafer together by using a first thermal or a thermo-anodic bonding process, such that the bonding interlayer is positioned between the III-V semiconductor wafer and the first major surface of the silicon wafer; removing a portion of the III-V semiconductor wafer from the second major surface of the III-V semiconductor wafer; and subjecting the III-V semiconductor wafer and the silicon wafer to a second thermal or thermo-anodic bonding process at a temperature less than approximately 200° C. after the step of removing a portion of the III-V semiconductor wafer.
Claim 3
Dependent Claim
24 words
The method of claim 1 further comprising removing a portion of the silicon wafer from the second major surface after the step of bonding.
Claim 4
Dependent Claim
21 words
The method of claim 1 wherein the step of bonding further comprises bonding at a temperature less than approximately 200° C.
Claim 5
Dependent Claim
109 words
The method of claim 1 further comprising the steps of: forming a plurality of trenches, each having a bottom, in the first major surface of the III-V semiconductor wafer before the step of forming the bonding interlayer such that the bonding interlayer is also formed in each of the plurality of trenches; forming a planarizable layer on the bonding interlayer on first major surface of the III-V semiconductor wafer and in the trenches; and wherein the step of removing a portion of the III-V semiconductor wafer further comprises removing a portion of the III-V semiconductor wafer down to at least the bottom of each of the plurality of trenches.
Claim 6
Dependent Claim
99 words
The method of claim 1 further comprising the steps of: forming a plurality of trenches, each having a bottom, in the first major surface of the III-V semiconductor wafer before the step of forming the bonding interlayer such that the bonding interlayer is also formed in each of the plurality of trenches; and wherein the step of removing a portion of the III-V semiconductor wafer further comprises removing a portion of the III-V semiconductor wafer to form a plurality of regions comprised of the III-V semiconductor wafer and the bonding interlayer, wherein the plurality of the regions have sidewalls.
Claim 7
Dependent Claim
27 words
The method of claim 5 further comprising altering the sidewalls of the plurality of regions so that the sidewalls are sloped at approximately a 45 degree angle.
Claim 8
Dependent Claim
37 words
The method of claim 1 wherein the step of forming the bonding interlayer comprises forming a layer or combination of layers selected from the list of silicon dioxide, doped silicon dioxide, silicon nitride, polysilicon, or amorphous silicon.
Claim 9
Dependent Claim
39 words
The method of claim 1 wherein the step of forming the bonding interlayer consists essentially of forming a layer or combination of layers selected from the list of silicon dioxide, doped silicon dioxide, silicon nitride, polysilicon, or amorphous silicon.
Claim 10
Dependent Claim
36 words
The method of claim 1 wherein the step of forming the bonding interlayer consists essentially of forming a silicon nitride layer on the III-V semiconductor wafer and a silicon dioxide layer on the silicon nitride layer.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-09-12 | 1998-03-14 | 1998-09-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-09-12 | 2002-03-14 | 2002-09-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-09-12 | 2006-03-14 | 2006-09-13 | $7700.00 | Window Closed / Lapsed |