Method to fabricate large capacitance capacitor in a semiconductor circuit

Claim 1

A method of fabricating a dynamic random access memory device having a high capacitance stacked capacitor comprising: forming a planarizing layer over a substrate having a source region; forming a first opening in said planarizing layer using a first photolithographic process; said first opening exposing said source region; said first opening formed using a first photolithographic process using a first optical mask having first optical openings; forming a polysilicon stud in said first opening; forming a dielectric layer over said planarizing layer; forming a second opening in said dielectric layer using a second photolithographic process using said first optical mask; forming a cylindrical electrode in said second opening; said polysilicon stud and said cylindrical electrodeforming a bottom electrode; selectively removing said dielectric layer; depositing a capacitor dielectric layer over said cylindrical electrode; patterning said capacitor dielectric layer so that portions remain covering at least the cylindrical electrode; and forming a top electrode over said capacitor dielectric layer.

Claim 2

A method of fabricating a dynamic random access memory device having a high capacitance stacked capacitor comprising: forming a planarizing layer over a substrate having a source region; forming a first opening in said planarizing layer using a first photolithographic process; said first opening exposing said source region; said first opening formed using a first photolithographic process using a first optical mask having first optical openings; forming a polysilicon stud in said first opening; forming a dielectric layer over said planarizing layer; forming a second opening in said dielectric layer using a second photolithographic process using said first optical mask; forming a cylindrical electrode in said second opening; said polysilicon stud and said cylindrical electrodeforming a bottom electrode; selectively removing said dielectric layer; depositing a capacitor dielectric layer over said cylindrical electrode; patterning said capacitor dielectric layer so that portions remain covering at least the cylindrical electrode; and forming a top electrode over said capacitor dielectric layer.

Claim 10

A method of fabricating a dynamic random access memory device including a high capacitance stacked capacitor on a semiconductor substrate having a field oxide region, a device region, a gate structure formed in the device region, an interconnection line formed over said field oxide region, and source/drain regions associated with the gate structure, a first insulating layer over portions of the device and field oxide region, an opening in the first insulating layer over source/drain regions where electrical contact is desired to the stacked capacitor, the method comprising: forming a planarizing layer over said first insulating layer; using a photolithographic process to form a first opening in said first insulating layer and said planarizing layer and exposing said source region; said first opening formed using a photolithographic process using a first optical mask having first optical openings; said photolithographic process comprising forming a first photoresist layer over said first insulating layer; exposing said first photoresist layer using said first optical mask, developing said first photoresist layer forming a first photoresist pattern having a first photoresist openings; etching said first insulating layer using said first photoresist pattern as an etch mask and forming said first opening in said first insulating layer exposing said source region; depositing a first polysilicon layer over said a planarizing layer; said first polysilicon layer filling said first opening and contacting said source region; planarizing said first polysilicon layer forming a polysilicon stud in said first opening; said planarization performed using a process selected from the group consisting of chemical-mechanical polishing and etching back; forming a dielectric layer over said planarizing layer; forming a second opening in said dielectric layer using a photolithographic process using said first optical mask; said photolithographic process comprising forming a second photoresist layer over said dielectric layer; exposing said second photoresist layer using said first optical mask; the exposure of said second photoresist layer having a higher energy than the exposure of said first photoresist layer; developing said second photoresist layer forming a second photoresist pattern having an second photoresist opening; etching said dielectric layer using said second photoresist pattern as an etch mask and forming said second opening in said dielectric layer wherein said etch exposes said polysilicon stud; said second opening defined by the sidewalls of said dielectric layer; said second opening having a larger open dimension than said first opening; forming a second polysilicon layer over said dielectric layer, over said sidewalls of said dielectric layer, and over said polysilicon stud; said second polysilicon layer defining a gap in said second opening; chemical-mechanical polishing said second polysilicon layer forming a cylindrical electrode; said polysilicon stud and said cylindrical electrodeforming a bottom electrode; selectively removing said dielectric layer; depositing a capacitor dielectric layer over the resulting surface; patterning said capacitor dielectric layerso that portions remain covering at least the bottom electrode; forming a top electrode over said capacitor dielectric layer; and forming passivation layers, metal lines, and contacts to complete the dynamic random access memory device.

Claim 11

A method of fabricating a dynamic random access memory device including a high capacitance stacked capacitor on a semiconductor substrate having a field oxide region, a device region, a gate structure formed in the device region, an interconnection line formed over said field oxide region, and source/drain regions associated with the gate structure, a first insulating layer over portions of the device and field oxide region, an opening in the first insulating layer over source/drain regions where electrical contact is desired to the stacked capacitor, the method comprising: forming a planarizing layer over said first insulating layer; using a photolithographic process to form a first opening in said first insulating layer and said planarizing layer and exposing said source region; said first opening formed using a photolithographic process using a first optical mask having first optical openings; said photolithographic process comprising forming a first photoresist layer over said first insulating layer; exposing said first photoresist layer using said first optical mask, developing said first photoresist layer forming a first photoresist pattern having a first photoresist openings; etching said first insulating layer using said first photoresist pattern as an etch mask and forming said first opening in said first insulating layer exposing said source region; depositing a first polysilicon layer over said a planarizing layer; said first polysilicon layer filling said first opening and contacting said source region; planarizing said first polysilicon layer forming a polysilicon stud in said first opening; said planarization performed using a process selected from the group consisting of chemical-mechanical polishing and etching back; forming a dielectric layer over said planarizing layer; forming a second opening in said dielectric layer using a photolithographic process using said first optical mask; said photolithographic process comprising forming a second photoresist layer over said dielectric layer; exposing said second photoresist layer using said first optical mask; the exposure of said second photoresist layer having a higher energy than the exposure of said first photoresist layer; developing said second photoresist layer forming a second photoresist pattern having an second photoresist opening; etching said dielectric layer using said second photoresist pattern as an etch mask and forming said second opening in said dielectric layer wherein said etch exposes said polysilicon stud; said second opening defined by the sidewalls of said dielectric layer; said second opening having a larger open dimension than said first opening; forming a second polysilicon layer over said dielectric layer, over said sidewalls of said dielectric layer, and over said polysilicon stud; said second polysilicon layer defining a gap in said second opening; chemical-mechanical polishing said second polysilicon layer forming a cylindrical electrode; said polysilicon stud and said cylindrical electrodeforming a bottom electrode; selectively removing said dielectric layer; depositing a capacitor dielectric layer over the resulting surface; patterning said capacitor dielectric layerso that portions remain covering at least the bottom electrode; forming a top electrode over said capacitor dielectric layer; and forming passivation layers, metal lines, and contacts to complete the dynamic random access memory device.