Communication circuit receiving data selectably synchronized to the rising or falling edge of a timing signal provided from the data source

Claim 2

A communication circuit that is controllably configured to receive a received signal from a first signal source when in a first operational mode and from a second signal source when in a second operational mode, comprising: data receiving means for receiving data items from the received signal, said received signal being in synchronization with a rising edge of a timing signal when in said first operational mode and being in synchronization with a decaying edge of the timing signal When in the second operational mode; and changeover means for changing via a software operation between the first operational mode when said received signal is received from the first signal source and the second operational mode when the received signal is received from the second operational source.

Claim 3

The communication circuit according to claim 1, wherein: said received signal transmits said data items therein so that said data items are successively transmitted and each item of said data items is maintained for a predetermined time period; and said changeover means provides a different time by delaying for another time period within said predetermined time period.

Claim 4

The communication circuit according to claim 2, wherein: said timing signal comprises a clock signal having serial clock pulses, said predetermined time period being a time between two adjacent same sort of edges of said serial clock pulses; said data receiving means for receiving respective of said data items from said received signal at a same sort of edge of said serial clock pulses; and said changeover means including an inverter for inverting said clock signal between a high level and a low level.

Claim 5

The communication circuit according to claim 2, wherein: said timing signal comprises a clock signal providing serial clock pulses, said predetermined time period being a time between two adjacent same sort of edges of said serial clock pulses; said data receiving means for receiving respective of said data items from said received signal at a same sort of edge of said serial clock pulses; and said changeover means comprises signal delaying means for delaying said receiving signal for a predetermined delay time.

Claim 6

The communication circuit according to claim 4, wherein said predetermined delay time comprises a time period between a first sort of edge of said serial clock pulses and a subsequent different sort of edge of said serial clock pulses.

Claim 7

The communication circuit according to claim 1, further comprising data putting means for putting said data items onto a transmitting signal at a time according to one of said timing signal or another timing signal.

Claim 8

The communication circuit according to claim 1, further comprising selecting means for selecting whether said changeover means is used for providing a different time at which said data receiving means receives said items of data according to whether another communication circuit to which said communication circuit connects uses said first operational mode or said second operational mode.

Claim 9

An integrated circuit comprising: a central processing unit that performs predetermined processing; a communication circuit that provides data communication between said central processing unit and another communication circuit that is external to said integrated circuit, comprising, data receiving means for receiving data items from a received signal at either a time according to a given timing signal or at a different time, said given timing signal being directly received by said data receiving means from another communication circuit; and time differing means for providing said different time to said data receiving means so that said data receiving means is configured to receive said data items when said another communication circuit uses a same timing convention or a different timing convention than said data receiving means.

Claim 10

An integrated circuit comprising: a central processing unit that performs predetermined processing; a communication circuit that provides data communication between said central processing unit and another communication circuit that is external to said integrated circuit, comprising, data receiving means for receiving data items from a received signal at either a time according to a given timing signal or at a different time, said given timing signal being directly received by said data receiving means from another communication circuit; and time differing means for providing said different time to said data receiving means so that said data receiving means is configured to receive said data items when said another communication circuit uses a same timing convention or a different timing convention than said data receiving means.

Claim 11

The communication circuit according to claim 8, further comprising selecting means for selecting whether said time differing means is used according to whether said another communication circuit uses said same timing convention or said different timing convention.

Claim 12

The integrated circuit according to claim 9, wherein said selecting means is for automatically selecting whether said time differing means is used by changing a software program.

Claim 13

The integrated circuit according to claim 8, wherein said communication circuit further comprises selecting means for selecting said given timing signal from one of a source external to said integrated circuit and an internal pulse generating circuit included in said integrated circuit.

Claim 14

The integrated circuit according to claim 11, wherein said selecting means is for automatically selecting whether said time differing means is used by changing a software program.

Claim 15

A communication circuit that is controllably configured to receive a received signal from a first signal source when in a first operational mode and from a second signal source when in a second operational mode, comprising: a timing signal input port that receives a timing signal having a falling edge and a decaying edge; a received signal input port that receives a received signal; a data selector circuit having, an input configured to receive said timing signal from said timing signal input port, a control signal input port, and an output port that outputs as an output clock signal a first clock signal when in said first operational mode and a second clock signal when in the second operational mode; and a software controllable control circuit configured to send a control signal to said control signal port of said data selector circuit, said control signal indicating a selection of either the first clock signal or the second clock signal so that said received signal is received in synchronization with a rising edge of said output clock signal when received from said first signal source and said received signal being in synchronization with a decaying edge of said output clock signal when received from said second signal source.

Claim 16

A communication circuit that is controllably configured to receive a received signal from a first signal source when in a first operational mode and from a second signal source when in a second operational mode, comprising: a timing signal input port that receives a timing signal having a falling edge and a decaying edge; a received signal input port that receives a received signal; a data selector circuit having, an input configured to receive said timing signal from said timing signal input port, a control signal input port, and an output port that outputs as an output clock signal a first clock signal when in said first operational mode and a second clock signal when in the second operational mode; and a software controllable control circuit configured to send a control signal to said control signal port of said data selector circuit, said control signal indicating a selection of either the first clock signal or the second clock signal so that said received signal is received in synchronization with a rising edge of said output clock signal when received from said first signal source and said received signal being in synchronization with a decaying edge of said output clock signal when received from said second signal source.

Claim 17

The circuit of claim 13, wherein said software controllable control circuit comprises a central processing unit connected to a data register, said central processing unit being configured to set a first data value in said data register when operating in said first operational mode and configured to set a second data value in said data register when operating in said second operational mode.

Claim 18

The circuit of claim 13, further comprising a serial to parallel converter configured to receive said received signal as a serial bit stream and output a parallel data word, said serial to parallel converter receiving data items in said received signal in synchronization with said output clock signal.

Claim 19

The circuit of claim 13, wherein said data selector comprises another input port and an inverter, said inverter being configured to invert a logic value of said timing signal so as to produce an inverted timing signal and apply said inverted timing signal to said another input port of said data selector.

Claim 20

The circuit of claim 13, further comprising an integrated circuit, said integrated circuit comprising said data selector circuit and said software controllable control circuit.

Claim 21

A communication circuit that is controllably configured to receive a received signal from a first signal source when in a first operational mode and from a second signal source when in a second operational mode, comprising: a timing signal input port that receives a timing signal having a falling edge and a decaying edge; a received signal input port that receives a received signal; a data selector circuit having, a first input configured to receive said received signal from said received signal input port, a second input configured to receive said received signal after being delayed by a predetermined time, a control signal input, and an output port that outputs said received signal when in said first operational mode and outputs said received signal after being delayed when in the second operational mode; and a software controllable control circuit that sends a control signal to said control signal port of said data selector circuit, said control signal selecting one of the received signal and the received signal after being delayed so that said received signal is received in synchronization with the rising edge of said timing signal when received from said first signal source and said received signal being in synchronization with the decaying edge of said timing signal when received from said second signal source.

Claim 22

A communication circuit that is controllably configured to receive a received signal from a first signal source when in a first operational mode and from a second signal source when in a second operational mode, comprising: a timing signal input port that receives a timing signal having a falling edge and a decaying edge; a received signal input port that receives a received signal; a data selector circuit having, a first input configured to receive said received signal from said received signal input port, a second input configured to receive said received signal after being delayed by a predetermined time, a control signal input, and an output port that outputs said received signal when in said first operational mode and outputs said received signal after being delayed when in the second operational mode; and a software controllable control circuit that sends a control signal to said control signal port of said data selector circuit, said control signal selecting one of the received signal and the received signal after being delayed so that said received signal is received in synchronization with the rising edge of said timing signal when received from said first signal source and said received signal being in synchronization with the decaying edge of said timing signal when received from said second signal source.

Claim 23

The communications circuit of claim 18, further comprising: a bidirectional timing signal port controllably configured to receive an external timing signal as said timing signal and output an internally generated timing signal for establishing another timing signal for use by a second communications circuit connected thereto; and a clock control signal configured to select the timing signal from between said external timing signal and said internally generated timing signal.