US5115455A
Expired / Lapsed
US
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Method and apparatus for stabilized data transmission
Assignee: Hewlett Packard Development Co LP
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Filing: 1990-06-29
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Granted: 1992-05-19
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Expires: 2010-06-29
Abstract
Abstract Data can be accurately transmitted between two subsystems in a synchronous system even if the clock skew or propagation delay between the two subsystems is greater than one clock cycle time. The source and destination subsystems are initialized to ensure synchronous operation. The source subsystem transmits data and a forwarded clock to the destination subsystem. The forwarded clock is passed through a delay device to introduce a one-half cycle delay into the forwarded clock timing. Data is captured in three state devices arranged in parallel to eliminate minimum delay requirements and to expand data valid time. The captured data is then aligned to the destination subsystem's clock by controlling a multiplexer which selects the proper signal at its input to pass to the input of a second state device coupled to its output. The data selected is then clocked into the second state device under the control of the distination subsystem's clock, thus aligning the received data with the destination subsystem's clock.
Inventors
- 👤 William A. Samaras
- 👤 David T. Vaughan
- 👤 Andrew D. Ingraham
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 08:43
CPC Classifications
H; H04; H04L; H04L7/00; H04L7/02; H04L7/033; H04L7/0337; H04L7/0338; G; G06; G06F; G06F1/00; G06F1/04; G06F1/10; H04L7/0008; H04L7/0016; H04L7/0033; H04L7/0037; H04L7/0041
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
333 words
A digital system which comprises: a first subsystem; a clock signal having a cycle time coupled by a clock path to the first subsystem; a second subsystem comprising: a plurality of latches arranged in parallel, each latch having a data input, control inputs and a data output, a multiplexer having a plurality of data inputs, each one coupled to the data output of one of the plurality of latches, control inputs, and an output, a state device having a data input coupled to the output of the multiplexer and a data output, and control logic having inputs and control outputs, each one of the outputs coupled to a preselected respective one of the control inputs of the plurality of latches and multiplexer, the second subsystem coupled to the clock signal; a data path coupling the first subsystem to the second subsystem for transmitting a series of data items from the first subsystem to the second subsystem; a forwarded clock path coupling the first subsystem to the second subsystem for transmitting a forwarded clock signal from the first subsystem to the second subsystem; a delay device intercoupled in the forwarded clock path between the first subsystem and the second subsystem, the delay device delaying the forwarded clock signal for a portion of the clock cycle time; the control logic generating a plurality of control signals in response to the delayed forwarded clock signal; the inputs of the plurality of latches coupled to the data path, the plurality of latches being sequentially enabled by the plurality of control signals from the control logic to capture the series of data items in the plurality of latches; the multiplexer sequentially selects its inputs to pass the series of data items available at the outputs of the plurality of latches to the multiplexer output under the control of the plurality of control signals from the control logic; and the state device captures the data items from the output of the multiplexer under the control of the clock signal.
Claim 2
Dependent Claim
333 words
A digital system which comprises: a first subsystem; a clock signal having a cycle time coupled by a clock path to the first subsystem; a second subsystem comprising: a plurality of latches arranged in parallel, each latch having a data input, control inputs and a data output, a multiplexer having a plurality of data inputs, each one coupled to the data output of one of the plurality of latches, control inputs, and an output, a state device having a data input coupled to the output of the multiplexer and a data output, and control logic having inputs and control outputs, each one of the outputs coupled to a preselected respective one of the control inputs of the plurality of latches and multiplexer, the second subsystem coupled to the clock signal; a data path coupling the first subsystem to the second subsystem for transmitting a series of data items from the first subsystem to the second subsystem; a forwarded clock path coupling the first subsystem to the second subsystem for transmitting a forwarded clock signal from the first subsystem to the second subsystem; a delay device intercoupled in the forwarded clock path between the first subsystem and the second subsystem, the delay device delaying the forwarded clock signal for a portion of the clock cycle time; the control logic generating a plurality of control signals in response to the delayed forwarded clock signal; the inputs of the plurality of latches coupled to the data path, the plurality of latches being sequentially enabled by the plurality of control signals from the control logic to capture the series of data items in the plurality of latches; the multiplexer sequentially selects its inputs to pass the series of data items available at the outputs of the plurality of latches to the multiplexer output under the control of the plurality of control signals from the control logic; and the state device captures the data items from the output of the multiplexer under the control of the clock signal.
Claim 3
Dependent Claim
27 words
The digital system of claim 1 wherein the portion of the clock cycle time the delay device delays the forwarded clock signal is one-half clock cycle time.
Claim 4
Dependent Claim
145 words
The digital system of claim 2 wherein the control logic comprises: a forwarded clock phase generator having inputs and control outputs, each one of the outputs coupled to a preselected respective one of the control inputs of the plurality of latches, the forwarded clock phase generator generating a plurality of control signals in response to the delayed forwarded clock signal to sequentially enable the plurality of latches to capture the series of data items; and data mux select logic having inputs and control outputs, each one of the outputs coupled to a preselected respective one of the control inputs of the multiplexer, the data mux select logic generating a plurality of selection control signals in response to the delayed version of the clock signal to sequentially select the inputs of the multiplexer to pass the series of data items to the output of the multiplexer.
Claim 5
Dependent Claim
386 words
A digital system which comprises: a first subsystem; a clock signal having a cycle time coupled by a clock path to the first subsystem; a second subsystem comprising: a plurality of latches arranged in parallel, each latch having a data input, control inputs and a data output, a multiplexer having a plurality of data inputs, each one coupled to the data output of one of the plurality of latches, control inputs, and an output, a state device having a data input coupled to the output of the multiplexer and a data output, a forwarded clock phase generator having inputs and control outputs, each one of the outputs coupled to a preselected respective one of the control inputs of the plurality of latches, and data mux select logic having inputs and control outputs, each one of the outputs coupled to a preselected respective one of the control inputs of the multiplexer, the second subsystem coupled to the clock signal; a data path coupling the first subsystem to the second subsystem for transmitting a series of data items from the first subsystem to the second subsystem; a forwarded clock path coupling the first subsystem to the second subsystem for transmitting a forwarded clock signal from the first subsystem to the second subsystem; a delay device intercoupled in the forwarded clock path between the first subsystem and the second subsystem, the delay device delaying the forwarded clock signal by a portion of the clock cycle time; the forwarded clock phase generator generating a plurality of control signals in response to the delayed forwarded clock signal; the data mux select logic generating a plurality of selection control signals in response to the clock signal; the inputs of the plurality of latches coupled to the data path, the plurality of latches being sequentially enabled by the plurality of control signals from the forwarded clock phase generator to capture the series of data items in the plurality of latches; the multiplexer sequentially selects its inputs to pass the series of data items available at the outputs of the plurality of latches to the multiplexer output under the control of the plurality of selection control signals from the data mux select logic; and the state device captures the data items from the output of the multiplexer under the control of the clock signal.
Claim 6
Dependent Claim
386 words
A digital system which comprises: a first subsystem; a clock signal having a cycle time coupled by a clock path to the first subsystem; a second subsystem comprising: a plurality of latches arranged in parallel, each latch having a data input, control inputs and a data output, a multiplexer having a plurality of data inputs, each one coupled to the data output of one of the plurality of latches, control inputs, and an output, a state device having a data input coupled to the output of the multiplexer and a data output, a forwarded clock phase generator having inputs and control outputs, each one of the outputs coupled to a preselected respective one of the control inputs of the plurality of latches, and data mux select logic having inputs and control outputs, each one of the outputs coupled to a preselected respective one of the control inputs of the multiplexer, the second subsystem coupled to the clock signal; a data path coupling the first subsystem to the second subsystem for transmitting a series of data items from the first subsystem to the second subsystem; a forwarded clock path coupling the first subsystem to the second subsystem for transmitting a forwarded clock signal from the first subsystem to the second subsystem; a delay device intercoupled in the forwarded clock path between the first subsystem and the second subsystem, the delay device delaying the forwarded clock signal by a portion of the clock cycle time; the forwarded clock phase generator generating a plurality of control signals in response to the delayed forwarded clock signal; the data mux select logic generating a plurality of selection control signals in response to the clock signal; the inputs of the plurality of latches coupled to the data path, the plurality of latches being sequentially enabled by the plurality of control signals from the forwarded clock phase generator to capture the series of data items in the plurality of latches; the multiplexer sequentially selects its inputs to pass the series of data items available at the outputs of the plurality of latches to the multiplexer output under the control of the plurality of selection control signals from the data mux select logic; and the state device captures the data items from the output of the multiplexer under the control of the clock signal.
Claim 7
Dependent Claim
26 words
The digital system of claim wherein the portion of the clock cycle time the delay device delays the forwarded clock signal is one-half clock cycle time.
Claim 8
Dependent Claim
406 words
A digital system which comprises: a first subsystem; a clock signal having a cycle time coupled by a clock path to the first subsystem; a second subsystem comprising: a plurality of latches arranged in parallel, each latch having a data input, control inputs and a data output, a multiplexer having a plurality of data inputs, each one coupled to the data output of one of the plurality of latches, control inputs, and an output, a state device having a data input coupled to the output of the multiplexer and a data output, a forwarded clock phase generator having inputs and control outputs, each one of the outputs coupled to a preselected respective one of the control inputs of the plurality of latches, and data mux select logic having inputs and control outputs, each one of the outputs coupled to a preselected respective one of the control inputs of the multiplexer, the second subsystem coupled to the clock signal providing a skewed version of the clock signal to the second subsystem; a data path coupling the first subsystem to the second subsystem for transmitting a series of data items from the first subsystem to the second subsystem; a forwarded clock path coupling the first subsystem to the second subsystem for transmitting a forwarded clock signal from the first subsystem to the second subsystem; a delay device intercoupled in the forwarded clock path between the first subsystem and the second subsystem, the delay device delaying the forwarded clock signal by a portion of the clock cycle time; the forwarded clock phase generator generating a plurality of control signals in response to the delayed forwarded clock signal; the data mux select logic generating a plurality of selection control signals in response to the skewed version of the clock signal in the second subsystem; the inputs of the plurality of latches coupled to the data path, the plurality of latches being sequentially enabled by the plurality of control signals from the forwarded clock phase generator to capture the series of data items in the plurality of latches; the multiplexer sequentially selects its inputs to pass the series of data items available at the outputs of the plurality of latches to the multiplexer output under the control of the plurality of selection control signals from the data mux select logic; and the state device captures the data items from the output of the multiplexer under the control of the clock signal.
Claim 9
Dependent Claim
406 words
A digital system which comprises: a first subsystem; a clock signal having a cycle time coupled by a clock path to the first subsystem; a second subsystem comprising: a plurality of latches arranged in parallel, each latch having a data input, control inputs and a data output, a multiplexer having a plurality of data inputs, each one coupled to the data output of one of the plurality of latches, control inputs, and an output, a state device having a data input coupled to the output of the multiplexer and a data output, a forwarded clock phase generator having inputs and control outputs, each one of the outputs coupled to a preselected respective one of the control inputs of the plurality of latches, and data mux select logic having inputs and control outputs, each one of the outputs coupled to a preselected respective one of the control inputs of the multiplexer, the second subsystem coupled to the clock signal providing a skewed version of the clock signal to the second subsystem; a data path coupling the first subsystem to the second subsystem for transmitting a series of data items from the first subsystem to the second subsystem; a forwarded clock path coupling the first subsystem to the second subsystem for transmitting a forwarded clock signal from the first subsystem to the second subsystem; a delay device intercoupled in the forwarded clock path between the first subsystem and the second subsystem, the delay device delaying the forwarded clock signal by a portion of the clock cycle time; the forwarded clock phase generator generating a plurality of control signals in response to the delayed forwarded clock signal; the data mux select logic generating a plurality of selection control signals in response to the skewed version of the clock signal in the second subsystem; the inputs of the plurality of latches coupled to the data path, the plurality of latches being sequentially enabled by the plurality of control signals from the forwarded clock phase generator to capture the series of data items in the plurality of latches; the multiplexer sequentially selects its inputs to pass the series of data items available at the outputs of the plurality of latches to the multiplexer output under the control of the plurality of selection control signals from the data mux select logic; and the state device captures the data items from the output of the multiplexer under the control of the clock signal.
Claim 10
Dependent Claim
27 words
The digital system of claim 6 wherein the portion of the clock cycle time the delay device delays the forwarded clock signal is one-half clock cycle time.
Claim 11
Dependent Claim
294 words
A subsystem which is a component of a synchronous digital system, the subsystem comprises: a plurality of latches arranged in parallel, each latch having a data input, control inputs and a data output; a multiplexer having a plurality of data inputs, each one coupled to the data output of one of the plurality of latches, control inputs, and an output; a state device having a data input coupled to the output of the multiplexer and a data output; control logic having inputs and control outputs, each one of the outputs coupled to a preselected respective one of the control inputs of the plurality of latches and multiplexer; a system clock signal having a cycle time coupled by a clock path to the subsystem; a data path coupled to the subsystem for receiving a series of data items; a forwarded clock path coupled to the subsystem for receiving a forwarded clock signal; a delay device intercoupled in the forwarded clock path, the delay device delaying the forwarded clock signal by a portion of the clock cycle time; the control logic generating a plurality of control signals in response to the delayed forwarded clock signal; the inputs of the plurality of latches coupled to the data path, the plurality of latches being sequentially enabled by the plurality of control signals from the control logic to capture the series of data items in the plurality of latches; the multiplexer sequentially selects its inputs to pass the series of data items available at the outputs of the plurality of latches to the multiplexer output under the control of the plurality of control signals from the control logic; and the state device captures the data items from the output of the multiplexer under the control of the clock signal.
Claim 12
Dependent Claim
294 words
A subsystem which is a component of a synchronous digital system, the subsystem comprises: a plurality of latches arranged in parallel, each latch having a data input, control inputs and a data output; a multiplexer having a plurality of data inputs, each one coupled to the data output of one of the plurality of latches, control inputs, and an output; a state device having a data input coupled to the output of the multiplexer and a data output; control logic having inputs and control outputs, each one of the outputs coupled to a preselected respective one of the control inputs of the plurality of latches and multiplexer; a system clock signal having a cycle time coupled by a clock path to the subsystem; a data path coupled to the subsystem for receiving a series of data items; a forwarded clock path coupled to the subsystem for receiving a forwarded clock signal; a delay device intercoupled in the forwarded clock path, the delay device delaying the forwarded clock signal by a portion of the clock cycle time; the control logic generating a plurality of control signals in response to the delayed forwarded clock signal; the inputs of the plurality of latches coupled to the data path, the plurality of latches being sequentially enabled by the plurality of control signals from the control logic to capture the series of data items in the plurality of latches; the multiplexer sequentially selects its inputs to pass the series of data items available at the outputs of the plurality of latches to the multiplexer output under the control of the plurality of control signals from the control logic; and the state device captures the data items from the output of the multiplexer under the control of the clock signal.
Claim 13
Dependent Claim
144 words
The subsystem of claim 8 wherein the control logic comprises: a forwarded clock phase generator having inputs and control outputs, each one of the outputs coupled to a preselected respective one of the control inputs of the plurality of latches, the forwarded clock phase generator generating a plurality of control signals in response to the delayed forwarded clock signal to sequentially enable the plurality of latches to capture the series of data items; and data mux select logic having inputs and control outputs, each one of the outputs coupled to a preselected respective one of the control inputs of the multiplexer, the data mux select logic generating a plurality of selection control signals in response to the delayed version of the clock signal to sequentially select the inputs of the multiplexer to pass the series of data items to the output of the multiplexer.
Claim 14
Independent Claim
226 words
A method of transmitting accurately a series of data items from a source subsystem to a destination subsystem, each of the source and destination subsystems being coupled to a clock signal having a clock cycle time, comprising the steps of: (a) transmitting the data items serially along a data path coupling the source subsystem to the destination subsystem; (b) transmitting a forwarded clock signal along a clock path coupling the source subsystem to the destination subsystem; (c) delaying the forwarded clock signal by a portion of the clock cycle time before the forwarded clock signal reaches the destination subsystem; (d) sequentially enabling a plurality of latches arranged in parallel in the destination subsystem as a function of the delayed forwarded clock to capture the data items being transmitted serially along the data path from the source subsystem in an interleaved manner through a continuous rotation among the plurality of latches; (e) sequentially passing the data items through the latches to inputs of a multiplexer as a function of the forwarded clock signal; (f) sequentially enabling the multiplexer to pass the data items at its inputs to its outputs; and (g) capturing each one of the data items from the output of the multiplexer in a state device within two clock cycle times from when each one of the data items was transmitted from the source subsystem.
Claim 15
Independent Claim
226 words
A method of transmitting accurately a series of data items from a source subsystem to a destination subsystem, each of the source and destination subsystems being coupled to a clock signal having a clock cycle time, comprising the steps of: (a) transmitting the data items serially along a data path coupling the source subsystem to the destination subsystem; (b) transmitting a forwarded clock signal along a clock path coupling the source subsystem to the destination subsystem; (c) delaying the forwarded clock signal by a portion of the clock cycle time before the forwarded clock signal reaches the destination subsystem; (d) sequentially enabling a plurality of latches arranged in parallel in the destination subsystem as a function of the delayed forwarded clock to capture the data items being transmitted serially along the data path from the source subsystem in an interleaved manner through a continuous rotation among the plurality of latches; (e) sequentially passing the data items through the latches to inputs of a multiplexer as a function of the forwarded clock signal; (f) sequentially enabling the multiplexer to pass the data items at its inputs to its outputs; and (g) capturing each one of the data items from the output of the multiplexer in a state device within two clock cycle times from when each one of the data items was transmitted from the source subsystem.
Claim 16
Independent Claim
237 words
A method of transmitting accurately a series of data items from a source subsystem to a destination subsystem, each of the source and destination subsystems being coupled to a clock signal having a clock cycle time, comprising the steps of: (a) initializing the source and destination subsystems to insure synchronous operation; (b) transmitting the data items serially along a data path coupling the source subsystem to the destination subsystem; (c) transmitting a forwarded clock signal along a clock path coupling the source subsystem to the destination subsystem; (d) delaying the forwarded clock signal by a portion of the clock cycle time before the forwarded clock signal reaches the destination subsystem; (e) sequentially enabling a plurality of latches arranged in parallel in the destination subsystem as a function of the delayed forwarded clock to capture the data items being transmitted serially along the data path from the source subsystem in an interleaved manner through a continuous rotation among the plurality of latches; (f) sequentially passing the data items through the latches to inputs of a multiplexer as a function of the forwarded clock signal; (g) sequentially enabling the multiplexer to pass the data items at its inputs to its outputs; and (h) capturing each one of the data items from the output of the multiplexer in a state device within two clock cycle times from when each one of the data items was transmitted from the source subsystem.
Claim 17
Independent Claim
237 words
A method of transmitting accurately a series of data items from a source subsystem to a destination subsystem, each of the source and destination subsystems being coupled to a clock signal having a clock cycle time, comprising the steps of: (a) initializing the source and destination subsystems to insure synchronous operation; (b) transmitting the data items serially along a data path coupling the source subsystem to the destination subsystem; (c) transmitting a forwarded clock signal along a clock path coupling the source subsystem to the destination subsystem; (d) delaying the forwarded clock signal by a portion of the clock cycle time before the forwarded clock signal reaches the destination subsystem; (e) sequentially enabling a plurality of latches arranged in parallel in the destination subsystem as a function of the delayed forwarded clock to capture the data items being transmitted serially along the data path from the source subsystem in an interleaved manner through a continuous rotation among the plurality of latches; (f) sequentially passing the data items through the latches to inputs of a multiplexer as a function of the forwarded clock signal; (g) sequentially enabling the multiplexer to pass the data items at its inputs to its outputs; and (h) capturing each one of the data items from the output of the multiplexer in a state device within two clock cycle times from when each one of the data items was transmitted from the source subsystem.
Claim 18
Independent Claim
29 words
The method of any one of claims 10 or 11 wherein the portion of the clock cycle time the forwarded clock signal is delayed is one-half clock cycle time.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-05-19 | 1995-11-18 | 1996-05-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-05-19 | 1999-11-18 | 2000-05-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-05-19 | 2003-11-18 | 2004-05-19 | $7700.00 | Window Closed / Lapsed |