Digital phase synchronizer

Claim 1

Apparatus for synchronizing a clock recovery signal to an incoming phase-varying digital signal (input signal), comprising; (a) state clock means to provide a bilevel signal of frequency N times the nominal frequency of said incoming signal where N is a selected even number; (b) memory means having a selected number of independently addressable addresses in which are stored corresponding selected different binary numbers each having a selected number M of binary bits; and M output leads equal in number to the number of bits in each stored word; (c) state latch means comprising M latch means responsive to said state clock for temporary storage of binary bits, said state latch means having at least M separate inputs to one of which each of the M output leads from said memory are connected; and means to set each of said M latch means on the rising transition of each cycle of said state clock; (d) received data latch and means to set said received data latch on the falling transition of each cycle of said state clock for sampling said input signal; (e) a selected number, say (M-Y) of the outputs of said M latches in said state latch means connected to M-Y input leads of said memory, the Yth output of said M latches carrying the output signal of said apparatus, where Y is the number of input and output signals; (f) the output of said received data latch connected to the Yth input lead to said memory means, each of the M input signals comprising M bits of a binary word defining the address of a selected storage location in said memory; whereby, dependent upon the particular polarities of the M input leads to said memory means, selected ones of the memory locations are determined and the M bit words stored therein are impressed on the M output leads, M-Y of which and the input signal are connected to the inputs of said state latch means, which are latched into said memory means on the next cycle of said state clock.