US4125869A
Expired / Lapsed
US
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Interconnect logic
Assignee: National Semiconductor Corp
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Filing: 1975-07-11
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Granted: 1978-11-14
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Expires: 1995-07-11
Abstract
Abstract The interconnect logic circuit for supplying input data to a register and recirculating data in the register includes a programmable logic array (PLA) and a recirculation control circuit connected between an output of the PLA and an input of the register and between an output and an input of the register. The recirculation control circuit includes a first transfer gate for sensing and storing information corresponding to the presence or absence of a command to supply input data, and a second transfer gate connected between an output and an input of the register and responsive to the stored information. The recirculation control circuit also includes a circuit for preventing the input data from being inputted to the PLA during a first time period, such that only a command to load that input data is sensed at an output of the PLA during that first time period. In the absence of a command to load input data into the register, the second transfer gate is enabled during a time period subsequent to the first time period to recirculate data in the register. In the presence of a command to load input data, the second transfer gate is disabled during the subsequent time period, the input data is passed through the PLA, and input data is supplied to the register. A method of channelling data to a register includes the steps of sensing the presence of a command to load input data for supplying such input data to the register, and sensing the absence of such a command to recirculate data in the register.
Inventors
- 👤 Manfred Gutmann
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 19:23
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/08; H03K19/094; H03K19/096; G; G06; G06F; G06F3/00; G06F3/007; G11; G11C; G11C19/00; G11C19/18; G11C19/182; G11C19/188; G11C19/28; G11C19/287
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
177 words
An interconnect circuit for supplying data to a register comprising (a) first means responsive to at least one command and to input data from external sources connected to respective inputs to said first means for supplying said command and simultaneously inhibiting said input data during a first time period and supplying said input data during a second time period at an output of said first means upon the condition that said one command is present during said first time period, (b) second means connected to said output for supplying said input data during said second time period to an input of said register upon the condition that said one command is present during said first time period and for supplying recirculation data to an input of said register, upon the condition that said one command is not present during said first time period, said recirculation data being derived at an output of said register; and (c) timing means connected to said first and second means for generating timing signals corresponding to said first and second time periods.
Claim 2
Dependent Claim
177 words
An interconnect circuit for supplying data to a register comprising (a) first means responsive to at least one command and to input data from external sources connected to respective inputs to said first means for supplying said command and simultaneously inhibiting said input data during a first time period and supplying said input data during a second time period at an output of said first means upon the condition that said one command is present during said first time period, (b) second means connected to said output for supplying said input data during said second time period to an input of said register upon the condition that said one command is present during said first time period and for supplying recirculation data to an input of said register, upon the condition that said one command is not present during said first time period, said recirculation data being derived at an output of said register; and (c) timing means connected to said first and second means for generating timing signals corresponding to said first and second time periods.
Claim 3
Dependent Claim
93 words
The interconnect logic of claim 1, wherein said second means includes a first transfer gate having inherent capacitance for storing data, said first transfer gate being connected to an output of said register, means for connecting an output of said first transfer gate to an input of said register, a second transfer gate for enabling said connecting means, connected between an output of said first means and said connecting means, and means for enabling said first transfer gate during said first time period and said second transfer gate during a second time period.
Claim 4
Dependent Claim
43 words
The interconnect logic of claim 2, further comprising a third transfer gate connected between an output of said first means and the input of said register, said enabling means further including means for enabling said third transfer gate during said second time period.
Claim 5
Dependent Claim
15 words
The interconnect logic of claim 3, wherein said connecting means includes a fourth transfer gate.
Claim 6
Dependent Claim
27 words
The interconnect logic of claim 4, wherein said second means further includes a pair of inverters connected between said second transfer gate and said fourth transfer gate.
Claim 7
Dependent Claim
14 words
The interconnect logic of claim 3, wherein said connecting means includes an OR gate.
Claim 8
Dependent Claim
41 words
The interconnect logic of claim 6, wherein said second means includes a fourth transfer device and a first inverter connected in series with one another and from an output of said second transfer gate to one input of said OR gate.
Claim 9
Dependent Claim
47 words
The interconnect logic of claim 7, wherein said second means includes a NAND gate having one input connected to an output of said OR gate, a second input connected to an output of said third transfer gate, and an output connected to the input of said register.
Claim 10
Dependent Claim
289 words
An interconnect circuit for supplying data to a register comprising (a) first means responsive to at least one command and to input data from external sources connected to respective inputs to said first means for supplying said command and simultaneously inhibiting said input data during a first time period and supplying said input data during a second time period at an output of said first means upon the condition that said one command is present during said first time period, (b) second means connected to said output for supplying said input data to an input of said register during said second time period upon the condition that said one command is present during said first time period and for supplying recirculation data to an input of said register during said second time period upon the condition that said one command is not present during said first time period, said recirculation data being derived at an output of said register; (c) timing means connected to said first and second means for generating a pair of timing signals which are out of phase with one another and correspond to said first and second time periods; and (d) means responsive to one of said timing signals for disabling said input data from being active at an input of said first means; said second means including: a first transfer gate connected between the output of said register and the input of said register, a second transfer gate connected to an output of said first means and responsive to said one timing signal for enabling said first transfer gate, and means connected between said first and said second transfer gates for storing a signal transmitted through said second transfer gate from said first means.
Claim 11
Dependent Claim
289 words
An interconnect circuit for supplying data to a register comprising (a) first means responsive to at least one command and to input data from external sources connected to respective inputs to said first means for supplying said command and simultaneously inhibiting said input data during a first time period and supplying said input data during a second time period at an output of said first means upon the condition that said one command is present during said first time period, (b) second means connected to said output for supplying said input data to an input of said register during said second time period upon the condition that said one command is present during said first time period and for supplying recirculation data to an input of said register during said second time period upon the condition that said one command is not present during said first time period, said recirculation data being derived at an output of said register; (c) timing means connected to said first and second means for generating a pair of timing signals which are out of phase with one another and correspond to said first and second time periods; and (d) means responsive to one of said timing signals for disabling said input data from being active at an input of said first means; said second means including: a first transfer gate connected between the output of said register and the input of said register, a second transfer gate connected to an output of said first means and responsive to said one timing signal for enabling said first transfer gate, and means connected between said first and said second transfer gates for storing a signal transmitted through said second transfer gate from said first means.
Claim 12
Dependent Claim
111 words
The interconnect circuit of claim 9, wherein said second means includes a first transfer gate responsive to a first timing phase signal and connected to an output of said register, means for connecting said first transfer gate to an input of said register, a second transfer gate responsive to a second timing phase signal and connected to the output of said first means for enabling said connecting means in response to the absence of said one command at the output of said first means, and a third transfer gate responsive to said first timing phase signal and connected from the output of said first means to the input of said register.
Claim 13
Dependent Claim
14 words
The interconnect circuit of claim 10, wherein said connecting means includes a transfer gate.
Claim 14
Dependent Claim
14 words
The interconnect circuit of claim 10, wherein said connecting means includes an OR gate.
Claim 15
Dependent Claim
47 words
The interconnect logic of claim 9, wherein said second means further includes means for storing an output signal from said first means, and means responsive to said storing means for enabling said first transfer gate during a second time period which occurs after said first time period.
Claim 16
Dependent Claim
88 words
The interconnect logic of claim 13, further comprising means for connecting an output of said first transfer gate to an input of said register, said enabling means including means for enabling said first transfer gate during said second timing phase, said first transfer gate including means for storing an output signal from said register when said first transfer date is enabled, and said storing means including means for enabling said connecting means upon the condition that a command is present at said output during said first timing phase.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1981-11-13 | 1982-05-15 | 1982-11-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1985-11-13 | 1986-05-15 | 1986-11-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1989-11-13 | 1990-05-15 | 1990-11-14 | $7700.00 | Window Closed / Lapsed |