US5724293A
Expired / Lapsed
US
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Semiconductor memory device having power line arranged in a meshed shape
Assignee: Mitsubishi Electric Corp
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Filing: 1997-03-14
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Granted: 1998-03-03
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Expires: 2017-03-14
Abstract
Abstract A semiconductor memory device includes a sense amp band including a plurality of sense amplifiers, and a plurality of operation power supply potential lines and a plurality of ground potential lines arranged in a meshed shape. The operation power supply potential lines and the ground potential lines include the lines arranged in parallel with and in proximity to the sense amp band. Each sense amplifier in the sense amp band is connected to an operation power supply potential line and a ground line arranged in proximity to and in parallel with the sense amplifier through a drive component. The drive component is provided one for a predetermined number of sense amplifiers, and is rendered conductive in response to a sense amplifier activation signal from a signal line arranged in parallel with the sense amp band. The plurality of operation power supply potential lines and the plurality of ground lines arranged in a meshed shape are contacted at crossings. Therefore, in the semiconductor memory device, no distribution of power supply potentials is generated to allow a stable supply of a power supply potential and a ground potential to an arbitrary circuit portion. In addition, since a sense amplifier is connected to a proximate operation power supply potential line and ground line through a drive component, a reliable and high-speed sensing operation is possible irrespective of a length of a sense amp drive signal line.
Inventors
- 👤 Shigeki Tomishima
- 👤 Mikio Asakura
- 👤 Kazutami Arimoto
- 👤 Hideto Hidaka
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 21:05
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/06; G11C5/00; G11C5/14
Claims Analysis
Total Claims: 19
Claim 1
Independent Claim
267 words
A semiconductor memory device comprising: a memory cell array including a plurality of memory cells arranged in rows and columns; a plurality of word lines each coupling a row of memory cells of said memory cell array; a plurality of pairs of bits lines, each of the pairs coupling a column of memory cells of said memory cell array; a first power supply line arranged in parallel with the bit lines, for transmitting a predetermined potential; a plurality of sense amplifiers provided corresponding to said plurality of pairs of bit lines respectively and arranged in parallel with said plurality of word lines, each of said plurality of sense amplifiers sensing and amplifying a potential difference between the bit lines of a corresponding bit line pair; an interconnection line transmitting a sense amplifier activation signal; a sense amplifier drive signal line transmitting a drive signal to said plurality of sense amplifiers; a second power supply line arranged in parallel with the word lines and coupled to said first power supply line; and a plurality of drive transistors provided such that a drive transistor is provided commonly to adjacent two sense amplifiers of said plurality of sense amplifiers, each of said plurality of drive transistors having a gate coupled to said interconnection line through a first contact hole between the bit lines of one of corresponding two bit line pairs, a source coupled to said second power supply line through a second contact hole provided between the bit lines of another of the corresponding two bit line pairs, and a drain coupled to said sense amplifier drive signal line.
Claim 2
Dependent Claim
267 words
A semiconductor memory device comprising: a memory cell array including a plurality of memory cells arranged in rows and columns; a plurality of word lines each coupling a row of memory cells of said memory cell array; a plurality of pairs of bits lines, each of the pairs coupling a column of memory cells of said memory cell array; a first power supply line arranged in parallel with the bit lines, for transmitting a predetermined potential; a plurality of sense amplifiers provided corresponding to said plurality of pairs of bit lines respectively and arranged in parallel with said plurality of word lines, each of said plurality of sense amplifiers sensing and amplifying a potential difference between the bit lines of a corresponding bit line pair; an interconnection line transmitting a sense amplifier activation signal; a sense amplifier drive signal line transmitting a drive signal to said plurality of sense amplifiers; a second power supply line arranged in parallel with the word lines and coupled to said first power supply line; and a plurality of drive transistors provided such that a drive transistor is provided commonly to adjacent two sense amplifiers of said plurality of sense amplifiers, each of said plurality of drive transistors having a gate coupled to said interconnection line through a first contact hole between the bit lines of one of corresponding two bit line pairs, a source coupled to said second power supply line through a second contact hole provided between the bit lines of another of the corresponding two bit line pairs, and a drain coupled to said sense amplifier drive signal line.
Claim 3
Dependent Claim
22 words
The semiconductor memory device according to claim 1, wherein said first power supply line is arranged extending over said memory cell array.
Claim 4
Dependent Claim
28 words
The semiconductor memory device according to claim 1, wherein said predetermined potential is a ground potential, and said plurality of drive transistors are N channel field effect transistors.
Claim 5
Dependent Claim
52 words
The semiconductor memory device according to claim 3, further comprising, an N channel drive transistor responsive to another sense amplifier activation signal different from said sense amplifier activation signal, for connecting said sense amplifier drive signal line to said second power supply line in a first stage of a sense amplifier operation.
Claim 6
Dependent Claim
110 words
The semiconductor memory device according to claim 1, further comprising, a third power supply line arranged in parallel with the bit lines, for transmitting an operation power supply potential, a second sense amplifier drive signal line for transmitting a second drive signal to said plurality of sense amplifiers, a second interconnection line transmitting a second sense amplifier activation signal, a fourth power supply line arranged in parallel with the word lines and coupled to said third power supply line, and a P channel drive transistor coupled between said fourth power supply line and said second sense amplifier drive signal line, and having a gate coupled to said second interconnection line.
Claim 7
Dependent Claim
40 words
The semiconductor memory device according to claim 5, further comprising, an equalize circuit for maintaining sense amplifier drive signal line and said second sense amplifier drive signal line at a predetermined reference potential in response to an equalize instruction signal.
Claim 8
Dependent Claim
178 words
The semiconductor memory device according to claim 1, further comprising: a third power supply line arranged in parallel with the bit lines, for transmitting an operation power supply line, a second sense amplifier drive signal line transmitting a second drive signal to said plurality of sense amplifiers, a second interconnection line transmitting a second sense amplifier activation signal, a fourth power supply line arranged in parallel with the word lines and coupled to said third power supply line, and a plurality of P channel drive transistors arranged such that a P channel drive transistor is provided commonly to adjacent two sense amplifiers, each of said plurality of P channel drive transistors having a gate coupled to said second interconnection line through a third contact hole provided between the bit lines of one of corresponding two bit line pairs, a source coupled to said fourth power supply line through a fourth contact hole provided between the bit lines of another of the corresponding two bit line pairs, and a drain coupled to said second sense amplifier drive signal line.
Claim 9
Dependent Claim
41 words
The semiconductor memory device according to claim 1, wherein each of the drive transistors is arranged between remote bit lines of corresponding two bit line pairs, said remote bit lines sandwiching adjacent bit lines in the corresponding two bit line pairs.
Claim 10
Dependent Claim
267 words
A semiconductor memory device comprising: a memory cell array including a plurality of memory cells arranged in rows and columns; a plurality of word lines each coupling a row of memory cells of said memory cell array; a plurality of pairs of bit lines, each of the pairs coupling a column of memory cells of said memory cell array; a first power supply line arranged in parallel with the bit lines, for transmitting a predetermined potential; a plurality of sense amplifiers provided corresponding to said plurality of pairs of bit lines respectively and arranged in parallel with said plurality of word lines, each of said plurality of sense amplifiers sensing and amplifying a potential difference between the bit lines of a corresponding bit line pair; an interconnection line transmitting a sense amplifier activation signal; a sense amplifier drive signal line transmitting a drive signal to said plurality of sense amplifiers; a second power supply line arranged in parallel with the word lines and coupled to said first power supply line; and a plurality of drive transistors provided such that a drive transistor is provided commonly to adjacent two sense amplifiers of said plurality of sense amplifiers, each of said plurality of drive transistors having a gate coupled to said interconnection line through a first contact hole between the bit lines of one of corresponding two bit line pairs, a source coupled to said second power supply line and a drain coupled to said sense amplifier drive signal line through a second contact hole provided between the bit lines of another of the corresponding two bit line pairs.
Claim 11
Dependent Claim
267 words
A semiconductor memory device comprising: a memory cell array including a plurality of memory cells arranged in rows and columns; a plurality of word lines each coupling a row of memory cells of said memory cell array; a plurality of pairs of bit lines, each of the pairs coupling a column of memory cells of said memory cell array; a first power supply line arranged in parallel with the bit lines, for transmitting a predetermined potential; a plurality of sense amplifiers provided corresponding to said plurality of pairs of bit lines respectively and arranged in parallel with said plurality of word lines, each of said plurality of sense amplifiers sensing and amplifying a potential difference between the bit lines of a corresponding bit line pair; an interconnection line transmitting a sense amplifier activation signal; a sense amplifier drive signal line transmitting a drive signal to said plurality of sense amplifiers; a second power supply line arranged in parallel with the word lines and coupled to said first power supply line; and a plurality of drive transistors provided such that a drive transistor is provided commonly to adjacent two sense amplifiers of said plurality of sense amplifiers, each of said plurality of drive transistors having a gate coupled to said interconnection line through a first contact hole between the bit lines of one of corresponding two bit line pairs, a source coupled to said second power supply line and a drain coupled to said sense amplifier drive signal line through a second contact hole provided between the bit lines of another of the corresponding two bit line pairs.
Claim 12
Dependent Claim
22 words
The semiconductor memory device according to claim 9, wherein said first power supply line is arranged extending over said memory cell array.
Claim 13
Dependent Claim
46 words
The semiconductor memory device according to claim 9, wherein each of said plurality of drive transistors has the source coupled to said second power supply line through a third contact hole provided between the bit lines of said another of the corresponding two bit line pairs.
Claim 14
Dependent Claim
28 words
The semiconductor memory device according to claim 9, wherein said predetermined potential is a ground potential, and said plurality of drive transistors are N channel field effect transistors.
Claim 15
Dependent Claim
178 words
The semiconductor memory device according to claim 12, further comprising, a third power supply line arranged in parallel with the bit lines, for transmitting an operation power supply line, a second sense amplifier drive signal line transmitting a second drive signal to said plurality of sense amplifiers, a second interconnection line transmitting a second sense amplifier activation signal, a fourth power supply line arranged in parallel with the word lines and coupled to said third power supply line, and a plurality of P channel drive transistors arranged such that a P channel drive transistor is provided commonly to adjacent two sense amplifiers, each of said plurality of P channel drive transistors having a gate coupled to said second interconnection line through a third contact hole provided between the bit lines of one of corresponding two bit line pairs, a source coupled to said fourth power supply line through a fourth contact hole provided between the bit lines of another of the corresponding two bit line pairs, and a drain coupled to said second sense amplifier drive signal line.
Claim 16
Dependent Claim
52 words
The semiconductor memory device according to claim 9, further comprising, an N channel drive transistor responsive to another sense amplifier activation signal different from said sense amplifier activation signal, for connecting said sense amplifier drive signal line to said second power supply line in a first stage of a sense amplifier operation.
Claim 17
Dependent Claim
110 words
The semiconductor memory device according to claim 9, further comprising, a third power supply line arranged in parallel with the bit lines, for transmitting an operation power supply potential, a second sense amplifier drive signal line for transmitting a second drive signal to said plurality of sense amplifiers, a second interconnection line transmitting a second sense amplifier activation signal, a fourth power supply line arranged in parallel with the word lines and coupled to said third power supply line, and a P channel drive transistor coupled between said fourth power supply line and said second sense amplifier drive signal line, and having a gate coupled to said second interconnection line.
Claim 18
Dependent Claim
40 words
The semiconductor memory device according to claim 15, further comprising, an equalize circuit for maintaining sense amplifier drive signal line and said second sense amplifier drive signal line at a predetermined reference potential in response to an equalize instruction signal.
Claim 19
Dependent Claim
41 words
The semiconductor memory device according to claim 9, wherein each of the drive transistors is arranged between remote bit lines of corresponding two bit line pairs, said remote bit lines sandwiching adjacent bit lines in the corresponding two bit line pairs.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-03-02 | 2001-09-01 | 2002-03-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-03-02 | 2005-09-01 | 2006-03-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-03-02 | 2009-09-01 | 2010-03-03 | $7700.00 | Window Closed / Lapsed |