Semiconductor memory device with sense amplifiers

Claim 1

A dynamic semiconductor memory device comprising: parallel bit line pairs formed on a substrate; first word lines extending substantially perpendicularly to said bit line pairs; a pair of second word lines extending substantially perpendicularly to said bit line pairs; memory cells formed at intersections between said bit line pairs and said first word lines and arranged in a matrix form; dummy cells formed at intersections between said bit line pairs and said second word lines; first sense amplifiers connected to said bit line pairs for performing a pre-sensing operation such that a potential difference between a specific bit line pair consisting of a bit line connected to a selected memory cell and a bit line connected to a dummy cell corresponding to the selected memory cell is detected and gradually amplified in a data readout mode for reading out data from the selected memory cell; second sense amplifiers connected to said bit line pairs, for performing a main sensing operation such that said potential difference of said specific bit line pair is further amplified in the data readout mode; and driver means connected to said first and second sense amplifiers for activating said first sense amplifiers simultaneously to perform the pre-sensing operation, and for then activating a selected one of said second sense amplifiers which is connected to said specific bit line pair to perform the main sensing operation, thereby reading out the data from the selected memory cell.