Patent US5723382A successfully refreshed from Google Patents.
US5723382A
Expired / Lapsed
US
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Method of making a low-resistance contact to silicon having a titanium silicide interface, an amorphous titanium nitride barrier layer and a conductive plug
Assignee: Individual
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Filing: 1995-07-31
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Granted: 1998-03-03
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Expires: 2015-07-31
Abstract
Abstract This invention constitutes a contact structure incorporating an amorphous titanium nitride barrier layer formed via low-pressure chemical vapor deposition (LPCVD) utilizing tetrakis-dialkylamido-titanium, Ti(NMe 2 ) 4 , as the precursor. The contact structure is fabricated by etching a contact opening through an dielectric layer down to a diffusion region to which electrical contact is to be made. Titanium metal is deposited over the surface of the wafer so that the exposed surface of the diffusion region is completely covered by a layer of the metal. At least a portion of the titanium metal layer is eventually converted to titanium silicide, thus providing an excellent conductive interface at the surface of the diffusion region. A titanium nitride barrier layer is then deposited using the LPCVD process, coating the walls and floor of the contact opening. Chemical vapor deposition of polycrystalline silicon, or of metal, such as tungsten, follows, and proceeds until the contact opening is completely filled with either polycrystalline silicon or metal.
Inventors
- 👤 Gurtej S. Sandhu
- 👤 Trung T. Doan
- 👤 Tyler A. Lowrey
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 03:17
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/01; H10W20/031; H10W20/032; H10W20/047; C; C23; C23C; C23C16/00; C23C16/22; C23C16/30; C23C16/34; H10P; H10P14/00; H10P14/40; H10P14/418; H10W20/033
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
143 words
A process for fabricating a low-resistance contact structure in an integrated semiconductor circuit which comprises the steps of: (a) providing a silicon region on an upper surface of a semiconductor wafer to which electrical contact must be made; (b) depositing a dielectric layer which overlies the silicon region; (c) etching a contact opening through said dielectric layer, said opening terminating at and exposing a portion of said silicon region; (d) depositing a titanium metal layer within the contact opening in order to cover the portion of the silicon region exposed by the contact opening; (e) depositing a amorphous titanium carbonitride film which lines the entire contact opening and overlies the titanium metal layer which covers the portion of the silicon region exposed by the contact opening; and (f) at least partially filling a remaining void within the contact opening with a conductive material.
Claim 2
Dependent Claim
143 words
A process for fabricating a low-resistance contact structure in an integrated semiconductor circuit which comprises the steps of: (a) providing a silicon region on an upper surface of a semiconductor wafer to which electrical contact must be made; (b) depositing a dielectric layer which overlies the silicon region; (c) etching a contact opening through said dielectric layer, said opening terminating at and exposing a portion of said silicon region; (d) depositing a titanium metal layer within the contact opening in order to cover the portion of the silicon region exposed by the contact opening; (e) depositing a amorphous titanium carbonitride film which lines the entire contact opening and overlies the titanium metal layer which covers the portion of the silicon region exposed by the contact opening; and (f) at least partially filling a remaining void within the contact opening with a conductive material.
Claim 3
Dependent Claim
27 words
The process of claim 1, wherein depositing the amorphous titanium carbonitride film is accomplished via a chemical vapor deposition process which takes place in a deposition chamber.
Claim 4
Dependent Claim
89 words
The process of claim 2, wherein during the chemical vapor deposition process, the chamber is evacuated to a pressure of less than 100 torr, the wafer is heated to a temperature within a range of 200°-600° C. which is maintained during the deposition process, and an organometallic precursor compound generally described as tetrakis-dialkylamido-titanium is admitted into the chamber, said precu thermal decomposition at or near the surface of the wafer, said thermal decomposition resulting in the deposition of the amorphous film on the wafer and within the contact opening.
Claim 5
Dependent Claim
13 words
The process of claim 3, wherein said precursor compound is, more specifically, tetrakis-dimethylamido-titanium.
Claim 6
Dependent Claim
23 words
The process of claim 1, wherein said conductive material is a metal selected from the group consisting of tungsten, aluminum, copper and nickel.
Claim 7
Dependent Claim
13 words
The process of claim 1, wherein said conductive material is doped polycrystalline silicon.
Claim 8
Dependent Claim
45 words
The process of claim 1, which further comprises the step of heating the wafer to cause at least a portion of the titanium layer, which overlies a diffusion region, to react with silicon atoms of the underlying diffusion region to form a titanium silicide layer.
Claim 9
Dependent Claim
38 words
The process of claim 7, wherein the reaction of at least a portion of the titanium metal layer with the silicon atoms of the underlying diffusion regions is induced prior to depositing the predominantly amorphous titanium carbonitride layer.
Claim 10
Dependent Claim
37 words
The process of claim 7, wherein the reaction of at least a portion of the titanium metal layer with the silicon atoms of the underlying diffusion regions is induced subsequent to depositing the amorphous titanium carbonitride layer.
Claim 11
Dependent Claim
40 words
The process of claim 1, which further comprises the step of subjecting the titanium carbonitride film to rapid thermal processing in an ambient containing one or more gasses selected from the group consisting of nitrogen, hydrogen and the noble gases.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-03-02 | 2001-09-01 | 2002-03-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-03-02 | 2005-09-01 | 2006-03-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-03-02 | 2009-09-01 | 2010-03-03 | $7700.00 | Window Closed / Lapsed |