US5721945A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Microprocessor configured to detect a DSP call instruction and to direct a DSP to execute a routine corresponding to the DSP call instruction
Assignee: Intellectual Ventures I LLC
•
Filing: 1996-05-06
•
Granted: 1998-02-24
•
Expires: 2016-05-06
Abstract
Abstract A microprocessor including an instruction decode unit configured to detect a DSP call instruction is provided. The DSP call instruction is indicative of a call to a subroutine which performs a DSP function. Detected DSP call instructions are routed to a DSP which executes a routine performing the corresponding function. Subsequent to the DSP completing execution of the routine, the microprocessor continues execution at the instruction subsequent to the DSP call instruction. If a DSP is not included in the computer system, the DSP call instruction is executed in a manner similar to a subroutine call instruction. The microprocessor subsequently executes a corresponding routine which performs the DSP function.
Inventors
- 👤 Andrew Mills
- 👤 Mark A. Ireton
- 👤 Thomas W. Lynch
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 18:21
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/38; G06F9/3885; G06F9/30145; G06F9/44; G06F9/448; G06F9/4482; G06F9/4484; G06F9/4486
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
256 words
A digital signal processing system comprising: a digital signal processing core; and a microprocessor core coupled to said digital signal processing core; wherein said microprocessor core comprises: an instruction cache configured to store instructions coded in a first instruction set for said microprocessor core, an instruction decode unit coupled to receive instructions from said instruction cache, wherein said instruction decode unit is configured to detect a DSP call instruction and generate a target address as an indication thereof, and an execute unit to execute instructions coded in said first instruction set for said microprocessor core, wherein said instruction decode unit is further configured to detect whether said digital signal processing core is enabled, and wherein said instruction decode unit is further configured to decode said DSP call instruction as a subroutine call instruction from said first instruction sat and dispatch it to said execute unit if said digital signal processing core is not enabled, thereby executing said DSP call instruction through a subroutine of instructions coded in said first instruction set for said microprocessor core; and wherein said digital signal processing core is configured to process said target address and to execute at least one instruction coded in a second instruction set for said digital signal processing core in response thereto, said at least one instruction being stored at a location in said digital signal processing core and being executed to implement a DSP function corresponding to said DSP call instruction, wherein said location in said digital signal processing core is dependent upon said target address.
Claim 2
Dependent Claim
256 words
A digital signal processing system comprising: a digital signal processing core; and a microprocessor core coupled to said digital signal processing core; wherein said microprocessor core comprises: an instruction cache configured to store instructions coded in a first instruction set for said microprocessor core, an instruction decode unit coupled to receive instructions from said instruction cache, wherein said instruction decode unit is configured to detect a DSP call instruction and generate a target address as an indication thereof, and an execute unit to execute instructions coded in said first instruction set for said microprocessor core, wherein said instruction decode unit is further configured to detect whether said digital signal processing core is enabled, and wherein said instruction decode unit is further configured to decode said DSP call instruction as a subroutine call instruction from said first instruction sat and dispatch it to said execute unit if said digital signal processing core is not enabled, thereby executing said DSP call instruction through a subroutine of instructions coded in said first instruction set for said microprocessor core; and wherein said digital signal processing core is configured to process said target address and to execute at least one instruction coded in a second instruction set for said digital signal processing core in response thereto, said at least one instruction being stored at a location in said digital signal processing core and being executed to implement a DSP function corresponding to said DSP call instruction, wherein said location in said digital signal processing core is dependent upon said target address.
Claim 3
Dependent Claim
56 words
The digital signal processing system as recited in claim 1 wherein said DSP call instruction comprises a displacement field of at least one byte, and wherein said instruction decode unit is configured to add said at least one byte to an address of a memory location storing said DSP call instruction to generate said target address.
Claim 4
Dependent Claim
104 words
The digital signal processing system as recited in claim 1 wherein said DSP call instruction comprises a displacement field as an index to a table stored in said instruction decode unit, said table being configured to store a plurality of target addresses, wherein said target address is stored within said table at said index, wherein each of said plurality of target addresses corresponds to one of a plurality of DSP program routines coded in said second instruction set for said digital signal processing core, and each of said plurality of DSP program routines executes at least one of a plurality of DSP call instructions.
Claim 5
Dependent Claim
67 words
The digital signal processing system as recited in claim 1 wherein said instruction decode unit comprises: a decoder circuit configured to detect said DSP call instruction and to generate said target address in response thereto; and a DSP dispatch circuit, said DSP dispatch circuit being coupled to said decoder circuit to receive said target address and to convey said target address to said digital signal processing core.
Claim 6
Dependent Claim
37 words
The digital signal processing system as recited in claim 1, wherein said digital processing core is included in an I/O device, and said I/O device being configured to communicate with said microprocessor core through an I/O bus.
Claim 7
Dependent Claim
33 words
The digital signal processing system as in claim 1, wherein said digital signal processing core comprises a storage for an operand for said at least one instruction coded in said second instruction set.
Claim 8
Dependent Claim
234 words
A digital signal processing system comprising: a microprocessor core having an instruction cache configured to store instructions coded in a first instruction set for said microprocessor core, and an instruction decode unit coupled to receive instructions from said instruction cache, wherein said instruction decode unit is configured to detect a DSP call instruction and generate a target address as an indication thereof; and a digital signal processing core coupled to said microprocessor core, wherein said digital signal processing core is configured to process said target address and to execute at least one instruction coded in a second instruction set for said digital signal processing core in response thereto, said at least one instruction being stored at a location in said digital signal processing core and being executed to implement a DSP function corresponding to said DSP call instruction, wherein said location in said digital signal processing core is dependent upon said target address, and wherein said microprocessor core and said digital signal processing core are fabricated in a single integrated circuit unit, wherein said instruction decode unit is configured to generate a different target address in response to detecting said DSP call instruction if said digital signal processing core is disabled, and wherein said microprocessor core further comprises a functional unit configured to process said different target address and to execute at least one instruction coded in said first instruction set in response thereto.
Claim 9
Dependent Claim
234 words
A digital signal processing system comprising: a microprocessor core having an instruction cache configured to store instructions coded in a first instruction set for said microprocessor core, and an instruction decode unit coupled to receive instructions from said instruction cache, wherein said instruction decode unit is configured to detect a DSP call instruction and generate a target address as an indication thereof; and a digital signal processing core coupled to said microprocessor core, wherein said digital signal processing core is configured to process said target address and to execute at least one instruction coded in a second instruction set for said digital signal processing core in response thereto, said at least one instruction being stored at a location in said digital signal processing core and being executed to implement a DSP function corresponding to said DSP call instruction, wherein said location in said digital signal processing core is dependent upon said target address, and wherein said microprocessor core and said digital signal processing core are fabricated in a single integrated circuit unit, wherein said instruction decode unit is configured to generate a different target address in response to detecting said DSP call instruction if said digital signal processing core is disabled, and wherein said microprocessor core further comprises a functional unit configured to process said different target address and to execute at least one instruction coded in said first instruction set in response thereto.
Claim 10
Dependent Claim
116 words
The digital signal processing system as recited in claim 7, wherein said microprocessor core further comprising an execute unit to execute instructions coded in said first instruction set for said microprocessor core, and wherein said instruction decode unit is further configured to detect whether said digital signal processing core is enabled, said instruction decode unit is further configured to decode said DSP call instruction as a subroutine call as a typical subroutine call instruction from said first instruction set and dispatch it to said execute unit if said digital signal processing core is not enabled, thereby executing said DSP call instruction through a subroutine of instructions coded in said first instruction set for said microprocessor core.
References Cited (Backward Citations)
US5193159A
Cited
US4949241A
Cited
US4979102A
Cited
US5119499A
Cited
US5588118A
Cited
US5577250A
Cited
US5603047A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-02-23 | 2001-08-25 | 2002-02-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-02-23 | 2005-08-25 | 2006-02-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-02-23 | 2009-08-25 | 2010-02-24 | $7700.00 | Window Closed / Lapsed |