Apparatus and method for synchronously providing a fullness indication of a dual ported buffer situated between two asynchronous buses

Claim 2

A circuit for generating a data buffer content indication of a dual ported data buffer device, the dual ported data buffer receiving a first address and a second address, said first address being synchronous to a first clock, said second address being synchronous to a second clock, the circuit comprising: a counter having a data input receiving said second address, a load input for receiving a load indication, a count enable input receiving a count indication, a clock input receiving said first clock, and a count output for providing a synchronous second address; a comparator having a first input receiving the second address, a second input receiving said synchronous second address and an output for providing a not equal indication; a flip-flop having a data input receiving said not equal indication, a clock input receiving said first clock, and a data output; a AND gate having one input connected to said flip-flop data output, a second input receiving said not equal indication and an output for providing said count indication; a flag generation means having a first input receiving said first address, a second input receiving said synchronous second address and an output for providing a data buffer content indication based on the difference between said addresses; and wherein said data buffer content indication is synchronous to said first clock.

Claim 3

The circuit of claim 1, wherein said data buffer content indication further includes providing a full indication when data is being written to the data buffer from the first bus, if said first bus address is greater than or equal to a sum of said synchronous second bus address added to said number of data locations.

Claim 4

The circuit of claim 1, wherein said data buffer content indication further includes providing an empty indication when said first bus is reading data from the data buffer, if said first bus address is less than said synchronous second bus address.

Claim 5

The circuit of claim 1, wherein the bridge further comprises: means for passing said first bus address to said second bus address, data and control providing means; and means for providing a load indication to said second bus address, data and control providing means when said first bus address is first provided and valid.

Claim 6

A bridge for coupling a primary bus to a secondary bus, the primary bus capable of being clocked asynchronously to the secondary bus, the bridge having a dual ported buffer for simultaneous read/write burst operations, the dual ported buffer having a primary interface and a secondary interface, the bridge further comprising: a primary bus counter coupled to the primary interface and responsive to a primary bus clock for providing an address to a first port of the dual ported buffer, said primary bus counter operable to load a first bus cycle address, said primary bus counter operable to increment the first bus cycle address according to a primary bus data cycle; a secondary bus counter coupled to the secondary interface and responsive to a secondary bus clock for providing an address to a second port of the dual ported buffer, said secondary bus counter operable to load the first bus cycle address, said secondary bus counter operable to increment the first bus cycle address according to a secondary bus data cycle; a secondary bus follower counter coupled to the primary interface and responsive to the primary bus clock for providing an address indicative of the address of said secondary bus counter, said secondary bus follower counter operable to load the first bus cycle address, said secondary bus follower counter responsive to a count indication to increment the first bus cycle address; a comparator operable to generate a difference indication based on the addresses of the primary and secondary bus counters, one of the addresses being a read address and the other of the addresses being a write address; a gating device responsive to the primary bus clock and operable to receive the difference indication and provide a count indication to the secondary bus follower counter if there is a difference in the addresses compared; and a status generator operable to generate a fullness indication of the dual ported buffer based on a difference between the addresses of said primary bus counter and said secondary bus follower counter, the fullness indication being provided synchronous to said primary bus.

Claim 7

A bridge for coupling a primary bus to a secondary bus, the primary bus capable of being clocked asynchronously to the secondary bus, the bridge having a dual ported buffer for simultaneous read/write burst operations, the dual ported buffer having a primary interface and a secondary interface, the bridge further comprising: a primary bus counter coupled to the primary interface and responsive to a primary bus clock for providing an address to a first port of the dual ported buffer, said primary bus counter operable to load a first bus cycle address, said primary bus counter operable to increment the first bus cycle address according to a primary bus data cycle; a secondary bus counter coupled to the secondary interface and responsive to a secondary bus clock for providing an address to a second port of the dual ported buffer, said secondary bus counter operable to load the first bus cycle address, said secondary bus counter operable to increment the first bus cycle address according to a secondary bus data cycle; a secondary bus follower counter coupled to the primary interface and responsive to the primary bus clock for providing an address indicative of the address of said secondary bus counter, said secondary bus follower counter operable to load the first bus cycle address, said secondary bus follower counter responsive to a count indication to increment the first bus cycle address; a comparator operable to generate a difference indication based on the addresses of the primary and secondary bus counters, one of the addresses being a read address and the other of the addresses being a write address; a gating device responsive to the primary bus clock and operable to receive the difference indication and provide a count indication to the secondary bus follower counter if there is a difference in the addresses compared; and a status generator operable to generate a fullness indication of the dual ported buffer based on a difference between the addresses of said primary bus counter and said secondary bus follower counter, the fullness indication being provided synchronous to said primary bus.

Claim 8

The bridge of claim 5, wherein if the first bus cycle is a burst read cycle, the address provided by said primary bus counter is a read address and the address provided by said secondary bus counter is a write address.

Claim 9

The bridge of claim 5, wherein if the first bus cycle is a burst write cycle, the primary bus data cycle and the secondary bus data cycle include a plurality of data cycles.

Claim 10

The bridge of claim 5, wherein if the first bus cycle is a read cycle the fullness indication indicates data availability in the dual ported buffer.

Claim 11

The bridge of claim 5, further including: a buffer depth register coupled to said status generator operable to store a programmable threshold value, and wherein if the first bus cycle is a write cycle the fullness indication indicates whether the dual ported buffer has reached the programmable threshold.

Claim 14

The method of claim 10, wherein if the first bus cycle is a burst read cycle, the address provided by said primary bus counter is a read address and the address provided by said secondary bus counter is a write address.

Claim 15

The method of claim 10, wherein if the first bus cycle is a burst write cycle, the primary bus data cycle and the secondary bus data cycle include a plurality of data cycles.

Claim 16

The method of claim 12, further comprising the step of: repeating the incrementing, comparing and generating steps for each data cycle if the bus cycle is a burst operation.

Claim 17

The method of claim 10, wherein if the first bus cycle is a read cycle the fullness indication indicates data availability in the dual ported buffer.

Claim 18

The method of claim 10, wherein the bridge further includes a buffer depth register for storing a programmable threshold value, the method further comprising the step of: loading a programmable threshold value in the buffer depth register, and wherein if the first bus cycle is a write cycle the fullness indication indicates whether the dual ported buffer has reached the programmable threshold.

Claim 19

A computer system having a primary bus and a secondary bus, the primary bus capable of being clocked asynchronously to the secondary bus, the computer system comprising: a processor coupled to the primary bus; a memory coupled to the primary bus; a hard disk system coupled to the secondary bus, the hard disk capable of burst operations with the memory; and a bridge coupled between the primary bus and the secondary bus, comprising: a dual ported buffer for simultaneous read/write burst operations, the dual ported buffer having a primary interface and a secondary interface; a primary bus counter coupled to the primary interface and responsive to a primary bus clock for providing an address to a first port of the dual ported buffer, said primary bus counter operable to load a first bus cycle address, said primary bus counter operable to increment the first bus cycle address according to a primary bus data cycle; a secondary bus counter coupled to the secondary interface and responsive to a secondary bus clock for providing an address to a second port of the dual ported buffer, said secondary bus counter operable to load the first bus cycle address, said secondary bus counter operable to increment the first bus cycle address according to a secondary bus data cycle; a secondary bus follower counter coupled to the primary interface and responsive to the primary bus clock for providing an address indicative of the address of said secondary bus counter, said secondary bus follower counter operable to load the first bus cycle address, said secondary bus follower counter responsive to a count indication to increment the first bus cycle address; a comparator operable to generate a difference indication based on the addresses of the primary and secondary bus counters, one of the addresses being a read address and the other of the addresses being a write address; a gating device responsive to the primary bus clock and operable to receive the difference indication and provide a count indication to the secondary bus follower counter if there is a difference in the addresses compared; and a status generator operable to generate a fullness indication of the dual ported buffer based on a difference between the addresses of said primary bus counter and said secondary bus follower counter, the fullness indication being provided synchronous to said primary bus.

Claim 20

A computer system having a primary bus and a secondary bus, the primary bus capable of being clocked asynchronously to the secondary bus, the computer system comprising: a processor coupled to the primary bus; a memory coupled to the primary bus; a hard disk system coupled to the secondary bus, the hard disk capable of burst operations with the memory; and a bridge coupled between the primary bus and the secondary bus, comprising: a dual ported buffer for simultaneous read/write burst operations, the dual ported buffer having a primary interface and a secondary interface; a primary bus counter coupled to the primary interface and responsive to a primary bus clock for providing an address to a first port of the dual ported buffer, said primary bus counter operable to load a first bus cycle address, said primary bus counter operable to increment the first bus cycle address according to a primary bus data cycle; a secondary bus counter coupled to the secondary interface and responsive to a secondary bus clock for providing an address to a second port of the dual ported buffer, said secondary bus counter operable to load the first bus cycle address, said secondary bus counter operable to increment the first bus cycle address according to a secondary bus data cycle; a secondary bus follower counter coupled to the primary interface and responsive to the primary bus clock for providing an address indicative of the address of said secondary bus counter, said secondary bus follower counter operable to load the first bus cycle address, said secondary bus follower counter responsive to a count indication to increment the first bus cycle address; a comparator operable to generate a difference indication based on the addresses of the primary and secondary bus counters, one of the addresses being a read address and the other of the addresses being a write address; a gating device responsive to the primary bus clock and operable to receive the difference indication and provide a count indication to the secondary bus follower counter if there is a difference in the addresses compared; and a status generator operable to generate a fullness indication of the dual ported buffer based on a difference between the addresses of said primary bus counter and said secondary bus follower counter, the fullness indication being provided synchronous to said primary bus.

Claim 21

The computer system of claim 16, wherein if the first bus cycle is a burst read cycle, the address provided by said primary bus counter is a read address and the address provided by said secondary bus counter is a write address.

Claim 22

The computer system of claim 16, wherein if the first bus cycle is a burst write cycle, the primary bus data cycle and the secondary bus data cycle include a plurality of data cycles.

Claim 23

The computer system of claim 16, wherein if the first bus cycle is a read cycle the fullness indication indicates data availability in the dual ported buffer.

Claim 24

The computer system of claim 16, wherein the bridge further includes: a buffer depth register coupled to said status generator operable to store a programmable threshold value, and wherein if the first bus cycle is a write cycle the fullness indication indicates whether the dual ported buffer has reached the programmable threshold.