Personal computer system with input/output controller having serial/parallel ports and a feedback line indicating readiness of the ports

Claim 2

A personal computer system comprising: a high speed local processor bus for passing data signals; a microprocessor operatively connected with said local processor bus for transfer of data signals therethrough; an option bus for receiving option cards and for passing data signals to and from any option card received; a planar I/O bus for passing data signals; a bus controller operatively connected with said local processor bus and said option bus and said planar I/O bus for controlling passage of data signals therebetween to and from said microprocessor; and an I/O controller having a plurality of segments, a first one of said segments providing a serial port for exchange of data signals with said local processor bus, a second one of said segments providing a parallel port for exchange of data signals with said local processor bus, and a third one of said segments providing a selectable interface for connection with a selected one of said option bus and said planar I/O bus, said third segment of said I/O controller further having a signal line for transmission of a feedback signal indicative of a readiness for transfer of data signals through one of said first and second segments of said I/O controller.

Claim 3

A personal computer system in accordance with claim 1 wherein said I/O controller is connected directly to said option bus.

Claim 4

A personal computer system in accordance with claim 1 wherein said I/O controller is connected directly to said planar I/O bus.

Claim 5

A personal computer system comprising: a high speed local processor bus for passing data signals; a microprocessor operatively connected with said local processor bus for transfer of data signals therethrough; an option bus for receiving option cards and for passing data signals to and from any option card received; a planar I/O bus for passing data signals; a bus controller operatively connected with said local processor bus and said option bus and said planar I/O bus for controlling passage of data signals therebetween to and from said microprocessor; and an I/O controller directly connected with said planar I/O bus and having a plurality of segments, a first one of said segments providing a serial port for exchange of data signals with said local processor bus, a second one of said segments providing a parallel port for exchange of data signals with said local processor bus, and a third one of said segments providing a selectable interface for connection with a selected one of said option bus and said planar I/O bus, said third segment having a signal line for transmission of a feedback signal indicative of a readiness for transfer of data signals through one of said first and second segments, said signal line being operatively connected with said bus controller for selectively indicating a readiness for transfer of data signals.

Claim 6

A personal computer system comprising: a high speed local processor bus for passing data signals; a microprocessor operatively connected with said local processor bus for transfer of data signals therethrough; an option bus for receiving option cards and for passing data signals to and from any option card received; a planar I/O bus for passing data signals; a bus controller operatively connected with said local processor bus and said option bus and said planar I/O bus for controlling passage of data signals therebetween to and from said microprocessor; and an I/O controller directly connected with said planar I/O bus and having a plurality of segments, a first one of said segments providing a serial port for exchange of data signals with said local processor bus, a second one of said segments providing a parallel port for exchange of data signals with said local processor bus, and a third one of said segments providing a selectable interface for connection with a selected one of said option bus and said planar I/O bus, said third segment having a signal line for transmission of a feedback signal indicative of a readiness for transfer of data signals through one of said first and second segments, said signal line being operatively connected with said bus controller for selectively indicating a readiness for transfer of data signals.

Claim 7

A personal computer system comprising: a high speed local processor bus for passing data signals; a microprocessor operatively connected with said local processor bus for transfer of data signals therethrough; an option bus for receiving option cards and for passing data signals to and from any option card received; a planar I/O bus for passing data signals; a bus controller operatively connected with said local processor bus and said option bus and said planar I/O bus for controlling passage of data signals therebetween to and from said microprocessor; and an I/O controller directly connected with said option bus and having a plurality of segments, a first one of said segments providing a serial port for exchange of data signals with said local processor bus, a second one of said segments providing a parallel port for exchange of data signals with said local processor bus, and a third one of said segments providing a selectable interface for connection with a selected one of said option bus and said planar I/O bus, said third segment having a signal line for transmission of a feedback signal indicative of a readiness for transfer of data signals through one of said first and second segments, said signal line being unconnected with any other component of said system for avoiding any interference with transfer of data signals.

Claim 8

A personal computer system comprising: a high speed local processor bus for passing data signals; a microprocessor operatively connected with said local processor bus for transfer of data signals therethrough; an option bus for receiving option cards and for passing data signals to and from any option card received; a planar I/O bus for passing data signals; a bus controller operatively connected with said local processor bus and said option bus and said planar I/O bus for controlling passage of data signals therebetween to and from said microprocessor; and an I/O controller directly connected with said option bus and having a plurality of segments, a first one of said segments providing a serial port for exchange of data signals with said local processor bus, a second one of said segments providing a parallel port for exchange of data signals with said local processor bus, and a third one of said segments providing a selectable interface for connection with a selected one of said option bus and said planar I/O bus, said third segment having a signal line for transmission of a feedback signal indicative of a readiness for transfer of data signals through one of said first and second segments, said signal line being unconnected with any other component of said system for avoiding any interference with transfer of data signals.