US5721690A
Expired / Lapsed
US
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Logic circuit synthesis
Assignee: NEC Corp
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Filing: 1995-08-18
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Granted: 1998-02-24
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Expires: 2015-08-18
Abstract
Abstract A method for a logic optimization in a logic synthesis comprises the following steps. Prior to an actual execution of a logic flattening process, a scale of unoptimized circuits is estimated assuming that the unoptimized circuits have already been subjected to the logical flattening. The unoptimized circuits are subjected to a two-level logic optimization only when an estimated scale of the unoptimized circuits exceeds a predetermined threshold value. Prior to an actual execution of a logic flattening process, a scale of the optimized circuits is estimated assuming that the optimized circuits have already been subjected to the logic flattening. The optimized circuits are subjected to the logic flattening if an estimated scale of the optimized circuits does not exceed the predetermined threshold value.
Inventors
- 👤 Toshiharu Asaka
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 03:16
CPC Classifications
G; G06; G06F; G06F30/00; G06F30/30; G06F30/32; G06F30/327
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
115 words
An apparatus for a logic synthesis comprising: a library input section that enters informations of a technology library block for technology mapping; a circuit input section that enters descriptions of a logic circuit to be subjected to a logic synthesis; a constraint condition input section that enters constraint conditions including at least any one of delay and area for said logic circuits; a logic optimization section that performs a two-level logic optimization during a flattening process; a technology mapping section that assigns said technology library block to logic circuits in consideration of the given constraint conditions as objective functions; and a circuit output section that output as circuits results of processes in said fifth step.
Claim 2
Independent Claim
115 words
An apparatus for a logic synthesis comprising: a library input section that enters informations of a technology library block for technology mapping; a circuit input section that enters descriptions of a logic circuit to be subjected to a logic synthesis; a constraint condition input section that enters constraint conditions including at least any one of delay and area for said logic circuits; a logic optimization section that performs a two-level logic optimization during a flattening process; a technology mapping section that assigns said technology library block to logic circuits in consideration of the given constraint conditions as objective functions; and a circuit output section that output as circuits results of processes in said fifth step.
Claim 3
Dependent Claim
24 words
The apparatus as claimed in claim 1, further comprising a memory section that stores any technology libraries, said logic circuits and said constraint conditions.
Claim 4
Dependent Claim
130 words
The apparatus as claimed in claim 1, wherein said logic optimization section is so arranged as to execute a process comprising the steps of: estimating, prior to an actual execution of a logic flattening process, a scale of unoptimized circuits assuming that said unoptimized circuits have already been subjected to said logical flattening; subjecting said unoptimized circuits to a two-level logic optimization only when an estimated scale of said unoptimized circuits exceeds a predetermined threshold value; estimating, prior to an actual execution of a logic flattening process, a scale of said optimized circuits, assuming that said optimized circuits have already been subjected to said logic flattening; and subjecting said optimized circuits to said logic flattening if an estimated scale of said optimized circuits does not exceed said predetermined threshold value.
Claim 5
Independent Claim
206 words
A method of executing two-level logic optimization of circuits during logic synthesis processes, said method comprising the steps of: extracting a circuit to be flattened; verifying whether said there remains any circuit to be flattened; executing, if there remains no further circuit to be flattened, a two-level logic optimization of said extracted circuit for subsequent multilevel realization; estimating, if there remains any further circuit to be flattened, a scale of said extracted circuit assuming that said extracted circuit were flattened; verifying whether said estimated scale of said circuit exceeds a threshold value; executing, if said estimated scale of said circuit does not exceed said threshold value, a flattening process of said circuit for subsequent returning to said extracting step for extracting another circuit; verifying, if said estimated scale of said circuit does exceed said threshold value, whether said two-level logic optimization has already been performed; returning to said extracting step for extracting another circuit, if said two-level logic optimization has already been performed; and executing, if said two-level logic optimization has not yet been performed, a two-level logic optimization for subsequent returning to said fourth step of estimating a scale of said circuit, wherein said steps are free of a step of evaluating of said circuit.
Claim 6
Independent Claim
206 words
A method of executing two-level logic optimization of circuits during logic synthesis processes, said method comprising the steps of: extracting a circuit to be flattened; verifying whether said there remains any circuit to be flattened; executing, if there remains no further circuit to be flattened, a two-level logic optimization of said extracted circuit for subsequent multilevel realization; estimating, if there remains any further circuit to be flattened, a scale of said extracted circuit assuming that said extracted circuit were flattened; verifying whether said estimated scale of said circuit exceeds a threshold value; executing, if said estimated scale of said circuit does not exceed said threshold value, a flattening process of said circuit for subsequent returning to said extracting step for extracting another circuit; verifying, if said estimated scale of said circuit does exceed said threshold value, whether said two-level logic optimization has already been performed; returning to said extracting step for extracting another circuit, if said two-level logic optimization has already been performed; and executing, if said two-level logic optimization has not yet been performed, a two-level logic optimization for subsequent returning to said fourth step of estimating a scale of said circuit, wherein said steps are free of a step of evaluating of said circuit.
Claim 7
Dependent Claim
31 words
The method as claimed in claim 4, wherein at least one of a number of product terms and of a number of fan-in is used as a scale of the circuits.
Claim 8
Dependent Claim
57 words
The method as claimed in claim 4, wherein an intermediate variable is provided with a flag indicating whether said two-level logic optimization has already been executed and wherein said flag indicating that said two-level logic optimization has already been executed is reset at an initialization to indicate that said two-level logic optimization has not yet been executed.
References Cited (Backward Citations)
US5029102A
Cited
US5461574A
Cited
US5572436A
Cited
US5287289A
Cited
US5500808A
Cited
JPH04352283A
Cited
US5473546A
Cited
US5452227A
Cited
US5493504A
Cited
US5436849A
Cited
US5517132A
Cited
US5537330A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-02-23 | 2001-08-25 | 2002-02-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-02-23 | 2005-08-25 | 2006-02-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-02-23 | 2009-08-25 | 2010-02-24 | $7700.00 | Window Closed / Lapsed |