Serial port controller for preventing repetitive interrupt signals

Claim 2

A controller for use with a serial port in a computer, said controller being utilized with a conventional universal asynchronous receiver/transmitter (UART), said UART being associated with said serial port, said UART including receiver and transmitter buffers, said controller comprising: an expanded buffer, said expanded buffer being operationally connected to a predetermined one of: said transmitter buffer for storing data to be transmitted to said UART via said serial port, or said receiver buffer of said UART for storing data received from said UART via said serial port; a scalable trigger circuit, said scalable trigger circuit being associated with said expanded buffer, for detecting when said data in said expanded buffer is equal to a predetermined trigger level and producing a service request signal each time said data in said expanded buffer is equal to said predetermined trigger level; and a timer responsive to said service request signal for providing an interrupt signal to said computer, said timer resetting said interrupt signal following servicing of said interrupt signal, said timer having a predetermined time-out period started by said servicing of said interrupt signal, said timer being non-responsive to a subsequent said service request signal by not sending a subsequent interrupt signal until said time-out period has elapsed.

Claim 3

A controller for use with a serial port in a computer, said controller being utilized with a conventional universal asynchronous receiver/transmitter (UART), said UART being associated with said serial port, said UART including receiver and transmitter buffers, said controller comprising: a first buffer, said first buffer being operationally connected to said transmitter buffer for storing data to be transmitted to said UART via said serial port; a first scalable trigger circuit, said first scalable trigger circuit being associated with said first buffer, for detecting when said data in said first buffer is equal to a predetermined trigger level and producing a service request signal in response thereto; a second buffer, said second buffer being operationally connected to said receiver buffer of said UART for storing data received from said UART via said serial port; a second scalable trigger circuit, said second scalable trigger circuit being associated with said second buffer, for detecting when said data in said second buffer is equal to a predetermined trigger level and producing a service request signal in response thereto; a service request queue buffer for receiving said service request signals from said first and second scalable trigger circuits for providing an interrupt signal to said computer; and a timer for resetting said interrupt signal following servicing of said interrupt signal, said timer having a predetermined time-out period started by said servicing of said interrupt signal, said timer preventing said service request queue buffer from providing a said interrupt signal in response to a subsequent said service request signal until said time-out period has elapsed.

Claim 4

A controller for use with a serial port in a computer, said controller being utilized with a conventional universal asynchronous receiver/transmitter (UART), said UART being associated with said serial port, said UART including receiver and transmitter buffers, said controller comprising: a first buffer, said first buffer being operationally connected to said transmitter buffer for storing data to be transmitted to said UART via said serial port; a first scalable trigger circuit, said first scalable trigger circuit being associated with said first buffer, for detecting when said data in said first buffer is equal to a predetermined trigger level and producing a service request signal in response thereto; a second buffer, said second buffer being operationally connected to said receiver buffer of said UART for storing data received from said UART via said serial port; a second scalable trigger circuit, said second scalable trigger circuit being associated with said second buffer, for detecting when said data in said second buffer is equal to a predetermined trigger level and producing a service request signal in response thereto; a service request queue buffer for receiving said service request signals from said first and second scalable trigger circuits for providing an interrupt signal to said computer; and a timer for resetting said interrupt signal following servicing of said interrupt signal, said timer having a predetermined time-out period started by said servicing of said interrupt signal, said timer preventing said service request queue buffer from providing a said interrupt signal in response to a subsequent said service request signal until said time-out period has elapsed.