Patent US5717324A successfully refreshed from Google Patents.
US5717324A
Expired / Lapsed
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Intermediate potential generation circuit
Assignee: Mitsubishi Electric Corp
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Filing: 1996-12-10
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Granted: 1998-02-10
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Expires: 2016-12-10
Abstract
Abstract An intermediate potential generation circuit having a controlled potential generation circuit including a voltage division circuit connected between a source potential node and a ground potential node, and generating first and second output potentials which deviate slightly from each other on both sides of the level of an intermediate potential. An N channel MOS transistor is connected between the source potential node and an intermediate potential output node, and has its gate receiving the potential corresponding to the first output potential. A P channel MOS transistor is connected between the intermediate potential output node and the ground potential node, and has its gate receiving the potential corresponding to the second output potential. The back gate of either one of the two MOS transistors is connected to the gate thereof.
Inventors
- 👤 Youichi Tobita
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 04:04
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G05; G05F; G05F1/00; G05F1/10; G05F1/46; G05F1/462; G05F1/465; G05F3/00; G05F3/02; G05F3/08; G05F3/10; G05F3/16; G05F3/20; G05F3/24; G05F3/242; G05F3/247; G11C5/00; G11C5/14; G11C5/145; G11C5/146; H; H03; H03H; H03H11/00; H03H11/02; H03H11/24; H03H11/245; H03K; H03K17/00; H03K17/06; H03K17/063
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
141 words
An intermediate potential generation circuit comprising: a controlled potential generation circuit including a voltage division circuit connected between a first potential node and a second potential node, and generating first and second output potentials; a first polarity MOS transistor connected between said first potential node and an intermediate potential output node, and having a gate receiving the potential corresponding to said first output potential; a second polarity MOS transistor connected between said intermediate potential output node and said second potential node, and having a gate receiving the potential corresponding to said second output potential; wherein the back gate of either one of the two MOS transistors is connected to the gate thereof, and the potential difference between said first potential node and second potential node is substantially equal to the summation of the respective threshold voltages of said both MOS transistors.
Claim 2
Dependent Claim
141 words
An intermediate potential generation circuit comprising: a controlled potential generation circuit including a voltage division circuit connected between a first potential node and a second potential node, and generating first and second output potentials; a first polarity MOS transistor connected between said first potential node and an intermediate potential output node, and having a gate receiving the potential corresponding to said first output potential; a second polarity MOS transistor connected between said intermediate potential output node and said second potential node, and having a gate receiving the potential corresponding to said second output potential; wherein the back gate of either one of the two MOS transistors is connected to the gate thereof, and the potential difference between said first potential node and second potential node is substantially equal to the summation of the respective threshold voltages of said both MOS transistors.
Claim 3
Dependent Claim
29 words
An intermediate potential generation circuit as set forth in claim 1, wherein the back gate of other one of the two MOS transistors is connected to the gate thereof.
Claim 4
Dependent Claim
31 words
An intermediate potential generation circuit as set forth in claim 1, wherein the back gate of other one of the two MOS transistors is connected to said intermediate potential output node.
Claim 5
Dependent Claim
30 words
An intermediate potential generation circuit as set forth in claim 1, wherein the back gate of other one of the two MOS transistors is connected to said first potential node.
Claim 6
Dependent Claim
59 words
An intermediate potential generation circuit as set forth in claim 1, said controlled potential generation circuit including in series: first and second resistors, each of which has substantially the same value of resistance; and at least two MOS transistors, each of which is diode-connected in the same forward direction and having a back gate connected to a gate thereof.
Claim 7
Dependent Claim
143 words
An intermediate potential generation circuit as set forth in claim 5, said controlled potential generation circuit comprising: a first series connected body connected between said first potential node and second potential node, including the first and second resistors and said at least two MOS transistors, which are of a first polarity; a second series connected body connected between said first potential node and second potential node, including at least two second polarity MOS transistors each of which is diode-connect in the same forward direction and having a back gate connected to a gate thereof and third and fourth resistors each of which has same value of resistance; and said first potential generation node is connected to a connecting point between said first and second resistors and said second potential generation node is connected to a connecting point between said third and fourth resistors.
Claim 8
Dependent Claim
85 words
An intermediate potential generation circuit as set forth in claim 5, said constant voltage generation circuit comprising; a series connected first resistor, first polarity MOS transistor, second polarity MOS transistor, and second resistor, connected between said first potential node and second potential node; wherein said first potential generation node is connected to a connecting point between said first resistor and first polarity MOS transistor, and said second potential generation node is connected to a connecting point between said second resister and second polarity MOS transistor.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-02-09 | 2001-08-11 | 2002-02-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-02-09 | 2005-08-11 | 2006-02-10 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-02-09 | 2009-08-11 | 2010-02-10 | $7700.00 | Window Closed / Lapsed |