Image processing system capable of high-speed and high-resolution image synthesis

Claim 2

An image processing system comprising: a plurality of image memories for storing image data; display means for displaying image data; display control means for effecting control for displaying the image data, stored in said plurality of image memories, on said display means; a system bus connected to each of said plurality of image memories and display control means for transferring image data, address data and control data; a first image bus connected to each of said plurality of image memories and display control means, for mutually transferring the image data and the address data; a second image bus connected to each of said plurality of image memories and said display control means for mutual high-speed transfer of the image data, wherein said second image bus transfers the image data in serial; and bus selection means in said display control means for selecting a desired one or more buses from among said system bus, said first image bus and said second image bus and for enabling transfer of the image, address and control data between said plurality of image memories and said display control means via the desired one or more selected bus or buses.

Claim 3

An image processing system according to claim 1, wherein said system bus is provided with system bus extension means and is connected to a system bus of a controller for controlling said system bus extension means and said entire system.

Claim 4

An image processing system according to claim 1, wherein said second image bus is connected to interface means for a scanner/printer for input or output of the image data, and said input or output is conducted by mutual transfer of the image data by said interface means and said image memories.

Claim 5

An image processing system according to claim 1, wherein said display control means comprises plural frame memories therein and is adapted to superimpose image data read from said plural image memories.

Claim 6

An image processing system according to claim 1, wherein said system bus and image transfer bus are connected to address calculator means for effecting image processing such as enlargement, reduction, displacement or rotation of the image data.

Claim 7

An image processing system according to claim 1, wherein said image memories comprise address generator means for transferring the image data to said second image bus.

Claim 8

An image processing apparatus according to claim 1, further comprising image data generating means connected to said system bus and first image bus, and adapted to generate and transfer image data to said image memories.

Claim 9

An image processing system comprising: a plurality of image memories for storing image data; display means for displaying image data; display control means for effecting control for displaying the image data, stored in said plurality of image memories, on said display means; a system bus connected to each of said plurality of image memories and display control means for transferring image data, address data and control data; a first image bus connected to each of said plurality of image memories and display control means, for transferring the image data and the address data; a second image bus connected to each of said plurality of image memories and said display control means for mutual high-speed transfer of the image data, wherein said second image bus transfers the image data in serial; bus selection means in said display control means for selecting a desired one or more buses from among said system bus, said first image bus and said second image bus and for enabling transfer of the image, address and control data between said plurality of image memories and said display control means via the desired one or more selected bus or buses; and control means connected to said system bus for controlling said plurality of image memories, said display means and said display control means to effect image processing.

Claim 10

An image processing system comprising: a plurality of image memories for storing image data; display means for displaying image data; display control means for effecting control for displaying the image data, stored in said plurality of image memories, on said display means; a system bus connected to each of said plurality of image memories and display control means for transferring image data, address data and control data; a first image bus connected to each of said plurality of image memories and display control means, for transferring the image data and the address data; a second image bus connected to each of said plurality of image memories and said display control means for mutual high-speed transfer of the image data, wherein said second image bus transfers the image data in serial; bus selection means in said display control means for selecting a desired one or more buses from among said system bus, said first image bus and said second image bus and for enabling transfer of the image, address and control data between said plurality of image memories and said display control means via the desired one or more selected bus or buses; and control means connected to said system bus for controlling said plurality of image memories, said display means and said display control means to effect image processing.

Claim 11

An image processing system according to claim 8, wherein said second image bus is connected to interface means for a scanner/printer for input or output of the image data, and said input or output is conducted by mutual transfer of the image data by said interface means and said image memories.

Claim 12

An image processing system according to claim 8, wherein said display control means comprises plural frame memories therein and is adapted to superimpose image data read from said plural image memories.

Claim 13

An image processing system according to claim 8, wherein said system bus and first image bus are connected to address calculator means for effecting image processings such as enlargement, reduction, displacement or rotation of the image data.

Claim 14

An image processing system according to claim 8, wherein said image memories comprise address generator means for transferring the image data to said second image bus.

Claim 15

An image processing system according to claim 8, further comprising image data generating means connected to said system bus and first image bus, and adapted to generate and transfer image data to said image memories.

Claim 16

An image processing system having a plurality of image memories for storing image data, display means for displaying image data, display control means for effecting control for displaying the image data, stored in said plurality of image memories, on said display means, and control means for controlling said plurality of image memories, said display means and said display control means, in which said plurality of image memories, said display control means and said control means are connected by a bus line for mutual transfer of image data and address data, said system comprising: an image bus line connected to each of said plurality of image memories and said display control means for mutual high-speed transfer of the image data, wherein said image bus line transfers the image data in serial; and bus selection means in said display control means for selecting a desired one of said bus line and said image bus line and for enabling transfer of the data between said plurality of image memories and said display control means via the desired one selected bus line, wherein said display control means includes a plurality of frame memories, and further includes means for processing image data stored in said plurality of frame memories.

Claim 17

An image processing system having a plurality of image memories for storing image data, display means for displaying image data, display control means for effecting control for displaying the image data, stored in said plurality of image memories, on said display means, and control means for controlling said plurality of image memories, said display means and said display control means, in which said plurality of image memories, said display control means and said control means are connected by a bus line for mutual transfer of image data and address data, said system comprising: an image bus line connected to each of said plurality of image memories and said display control means for mutual high-speed transfer of the image data, wherein said image bus line transfers the image data in serial; and bus selection means in said display control means for selecting a desired one of said bus line and said image bus line and for enabling transfer of the data between said plurality of image memories and said display control means via the desired one selected bus line, wherein said display control means includes a plurality of frame memories, and further includes means for processing image data stored in said plurality of frame memories.