Affine conversion apparatus using a raster generator to reduce cycle time

Claim 1

An image processing apparatus comprising: an affine conversion address generator for generating an image data read affine conversion address based on a raster address and outputting image memory read and write signals; a first image memory for storing original image data; a second image memory for storing an affine-converted image data corresponding to an affine converted version of said original image data; a control bus, connected to said affine conversion address generator and said first and second image memories, for conducting and transferring the image data read affine conversion address and the read and write signals from said affine conversion generator to said first and second memories; an image bus, connected to said first and second image memories, for operating independently of said control bus in order to transfer the image data output from said first image memory to said second memory; first image memory control means, coupled to said first image memory and to said image bus, for reading out the original image data from said first image memory, outputting the original image data onto said image bus, and for selectively producing a busy signal for said image bus, in response to the affine conversion address output from said affine conversion address generator and the read signal, wherein said image bus is also for transferring said busy signal from said first image memory control means; and second image memory control means, coupled to said second image memory and to said image bus, for storing, in response to the busy signal on said image bus, the original image data on said image bus in accordance with the raster address, said original data stored at said raster address constituting said affine-converted image data.