Semiconductor memory device having a transistor, a bit line, a word line and a stacked capacitor

Claim 2

A semiconductor memory configuration, comprising single-transistor memory cells, each memory cell including: a semiconductor substrate; another layer disposed above said semiconductor substrate; a transistor being disposed in said semiconductor substrate and having first and second source/drain regions or S/D regions; a bit line disposed in a bit line level above said transistor and enclosing an angle with an active region of said transistor; an insulating cover being disposed on said bit line in said other layer and having an upper surface; a capacitor being disposed above said bit line and having a lower capacitor plate disposed on said other layer; a one-piece transistor/capacitor pillar or TC pillar electrically connecting said first S/D region to said lower capacitor plate and having an upper surface; a one-piece transistor bit-line pillar or TB pillar electrically connecting said second S/D region to said bit line; further conductor tracks in said bit-line level; a substrate pillar or SB pillar electrically connecting said further conductor tracks to said semiconductor substrate; said TB pillar and said SB pillar having upper surfaces being chemically-mechanically polished and disposed in one completely planarized surface; and said upper surface of said insulating cover and said upper surface of said TC pillar being disposed in another completely planarized surface.

Claim 3

The semiconductor memory configuration according to claim 1, wherein said other layer disposed above said semiconductor substrate is an insulating layer.

Claim 4

The semiconductor memory configuration according to claim 1, wherein said other layer disposed above said semiconductor substrate is a planarization layer.

Claim 5

A semiconductor memory configuration, comprising single-transistor memory cells, each memory cell including: a semiconductor substrate; another layer disposed above said semiconductor substrate; a transistor being disposed in said semiconductor substrate and having first and second source/drain regions or S/D regions; a bit line disposed in a bit line level above said transistor and enclosing an angle with an active region of said transistor; an insulating cover being disposed on said bit line in said other layer and having an upper surface; a capacitor being disposed above said bit line and having a lower capacitor plate disposed on said other layer; a transistor/capacitor pillar or TC pillar electrically connecting said first S/D region to said lower capacitor plate and having an upper surface; a transistor bit-line pillar or TB pillar electrically connecting said second S/D region to said bit line; further conductor tracks in said bit-line level; further underlying conductor tracks disposed in a word-line plane below said bit-line level; a word-line pillar or WB pillar electrically connecting said further conductor tracks to said further underlying conductor tracks, said WB pillar and said TB pillar having upper surfaces being chemically-mechanically polished and disposed in said one completely planarized surface; and said upper surface of said insulating cover and said upper surface of said TC pillar being disposed in another completely planarized surface.

Claim 6

A semiconductor memory configuration, comprising single-transistor memory cells, each memory cell including: a semiconductor substrate; another layer disposed above said semiconductor substrate; a transistor being disposed in said semiconductor substrate and having first and second source/drain regions or S/D regions; a bit line disposed in a bit line level above said transistor and enclosing an angle with an active region of said transistor; an insulating cover being disposed on said bit line in said other layer and having an upper surface; a capacitor being disposed above said bit line and having a lower capacitor plate disposed on said other layer; a transistor/capacitor pillar or TC pillar electrically connecting said first S/D region to said lower capacitor plate and having an upper surface; a transistor bit-line pillar or TB pillar electrically connecting said second S/D region to said bit line; further conductor tracks in said bit-line level; further underlying conductor tracks disposed in a word-line plane below said bit-line level; a word-line pillar or WB pillar electrically connecting said further conductor tracks to said further underlying conductor tracks, said WB pillar and said TB pillar having upper surfaces being chemically-mechanically polished and disposed in said one completely planarized surface; and said upper surface of said insulating cover and said upper surface of said TC pillar being disposed in another completely planarized surface.

Claim 7

A semiconductor memory configuration, comprising single-transistor memory cells, each memory cell including: a semiconductor substrate; another layer disposed above said semiconductor substrate; a transistor being disposed in said semiconductor substrate and having first and second source/drain regions or S/D regions; a bit line disposed in a bit line level above said transistor and enclosing an angle with an active region of said transistor; an insulating cover being disposed on said bit line in said other layer and having an upper surface; a capacitor being disposed above said bit line and having a lower capacitor plate disposed on said other layer; a transistor/capacitor pillar or TC pillar electrically connecting said first S/D region to said lower capacitor plate and having an upper surface; a transistor bit-line pillar or TB pillar electrically connecting said second S/D region to said bit line; further conductor tracks in said bit-line level; a substrate pillar or SB pillar electrically connecting said further conductor tracks to said semiconductor substrate; further underlying conductor tracks disposed in a word-line plane below said bit-line-level; a word-line pillar or WB pillar electrically connecting said further conductor tracks to said further underlying conductor tracks; said TB, SB and WB pillars having upper surfaces being chemically-mechanically polished and disposed in said one completely planarized surface; and said upper surface of said insulating cover and said upper surface of said TC pillar being disposed in another completely planarized surface.

Claim 8

A semiconductor memory configuration, comprising single-transistor memory cells, each memory cell including: a semiconductor substrate; another layer disposed above said semiconductor substrate; a transistor being disposed in said semiconductor substrate and having first and second source/drain regions or S/D regions; a bit line disposed in a bit line level above said transistor and enclosing an angle with an active region of said transistor; an insulating cover being disposed on said bit line in said other layer and having an upper surface; a capacitor being disposed above said bit line and having a lower capacitor plate disposed on said other layer; a transistor/capacitor pillar or TC pillar electrically connecting said first S/D region to said lower capacitor plate and having an upper surface; a transistor bit-line pillar or TB pillar electrically connecting said second S/D region to said bit line; further conductor tracks in said bit-line level; a substrate pillar or SB pillar electrically connecting said further conductor tracks to said semiconductor substrate; further underlying conductor tracks disposed in a word-line plane below said bit-line-level; a word-line pillar or WB pillar electrically connecting said further conductor tracks to said further underlying conductor tracks; said TB, SB and WB pillars having upper surfaces being chemically-mechanically polished and disposed in said one completely planarized surface; and said upper surface of said insulating cover and said upper surface of said TC pillar being disposed in another completely planarized surface.

Claim 9

The semiconductor memory configuration according to claim 1, including an edge insulation insulating said bit line from part of said TC pillar.

Claim 10

The semiconductor memory configuration according to claim 1, including a bit-line contact hole through which said bit line is connected to said TB pillar.

Claim 11

The semiconductor memory configuration according to claim 1, wherein said lower capacitor plate has upper surfaces being polished and disposed in a completely planarized surface.

Claim 12

The semiconductor memory configuration according to claim 1, including peripheral regions and cell arrays having upper surfaces being polished and disposed in a completely planarized surface.

Claim 13

The semiconductor memory configuration according to claim 4, wherein said other layer disposed above said semiconductor substrate is an insulating layer.

Claim 14

The semiconductor memory configuration according to claim 4, wherein said other layer disposed above said semiconductor substrate is a planarization layer.

Claim 15

The semiconductor memory configuration according to claim 4, including an edge insulation insulating said bit line from part of said TC pillar.

Claim 16

The semiconductor memory configuration according to claim 4, including a bit-line contact hole through which said bit line is connected to said TB pillar.

Claim 17

The semiconductor memory configuration according to claim 4, wherein said lower capacitor plate has upper surfaces being polished and disposed in a completely planarized surface.

Claim 18

The semiconductor memory configuration according to claim 4, including peripheral regions and cell arrays having upper surfaces being polished and disposed in a completely planarized surface.