Shared memory graphics accelerator system

Claim 1

An integrated graphics display memory element utilizable in a graphics accelerator system that provides graphics display data to a display element for display thereby, wherein the graphics accelerator system includes a central processing unit that generates graphics display data and graphics commands for processing graphics display data and an off-chip frame buffer memory element having a first refresh frequency requirement, the integrated graphics display memory element comprising: a graphics accelerator that can be connected to receive graphics display data and graphics commands from the central processing unit via a CPU data bus and a control signal bus, respectively; a data distribution bus connected to the graphics accelerator; an on-chip frame buffer memory element connected to the data distribution bus for receiving graphics display data from the graphics accelerator; an output data storage element connected to the data distribution bus for receiving graphics display data from the graphics accelerator and the on-chip frame buffer memory element as output display data, the off-chip frame buffer memory element being connectable to the data distribution bus for providing graphics display data to the output data storage element as output display data, and wherein the on-chip frame buffer memory element has a second refresh frequency requirement lower than the first refresh frequency of the off-chip frame buffer element.