Patent US5710744A successfully refreshed from Google Patents.
US5710744A
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Timing generator for IC testers
Assignee: Advantest Corp
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Filing: 1996-05-23
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Granted: 1998-01-20
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Expires: 2016-05-23
Abstract
Abstract Output pulses of a period which is an integral multiple of the fundamental period T are generated by coarse timing generating means 13 in correspondence with an integral part Di of timing set data read out of a memory 11, and the output pulses are distributed by distributing means 17 to set- and reset-side delay means 26s and 26r under the control of a waveform generation control circuit 18. Pieces of data Dr and Ds, which are obtained by adding a fractional part of the timing set data read out of the memory and set-side skew absorbing data and reset-side skew absorbing data, respectively, are provided as delay control signals to the set- and reset-side delay means 26s and 26r. The pulse distributed to the set-side delay means 26s is delayed by logical delay means 27s for any one of delay times 0, 1T and 2T in accordance with the integral value of the data Ds, and the thus delayed pulse is further delayed by fine delay means 28s in accordance with the fractional value of the data Ds. Similarly, the pulse distributed to the reset-side delay means 26r is delayed by logical delay means 27r in accordance with the integral value of the data Dr and then delayed by fine delay means 28r in accordance with the fractional value of the data Dr. The outputs from the fine delay means 28s and 28r are applied to a flip-flop 25 to set and reset it to generate the waveform of a desired pattern.
Inventors
- 👤 Masakatsu Suda
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 14:42
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/319; G01R31/31917; G01R31/31922; H; H03; H03K; H03K5/00; H03K5/13; G01R31/26; G01R31/3183; H03K5/131; H03K5/135; H10; H10P; H10P74/00
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
172 words
A timing generator for IC testers which is provided for each pin of an IC device under test, comprising: coarse timing generating means for generating pulses of a period which is an integral multiple of a fundamental period corresponding to an integral part of timing set data expressed in terms of said fundamental period; distributing means for distributing said pulses to set- and reset-sides in accordance with the output from a waveform generation control circuit; set-side delay means for delaying said pulse distributed to said set-side by a time interval corresponding to data obtained by adding a fractional part of said timing set data and data which is generated at a post-stage of said timing generator for compensating for set-side propagation delay variations; and reset-side delay means for delaying said pulse distributed to said reset-side by a time interval corresponding to data obtained by adding said fractional part of said timing set data and data which is generated at said post-stage of said timing generator for compensating for reset-side propagation delay variations.
Claim 2
Dependent Claim
172 words
A timing generator for IC testers which is provided for each pin of an IC device under test, comprising: coarse timing generating means for generating pulses of a period which is an integral multiple of a fundamental period corresponding to an integral part of timing set data expressed in terms of said fundamental period; distributing means for distributing said pulses to set- and reset-sides in accordance with the output from a waveform generation control circuit; set-side delay means for delaying said pulse distributed to said set-side by a time interval corresponding to data obtained by adding a fractional part of said timing set data and data which is generated at a post-stage of said timing generator for compensating for set-side propagation delay variations; and reset-side delay means for delaying said pulse distributed to said reset-side by a time interval corresponding to data obtained by adding said fractional part of said timing set data and data which is generated at said post-stage of said timing generator for compensating for reset-side propagation delay variations.
Claim 3
Dependent Claim
212 words
The timing generator of claim 1, further comprising: a memory which stores said integral part of said timing set data, said set-side added data and said reset-side added data and is read every test cycle, said integral part read out of said memory being provided to said coarse timing generating means; wherein said set-side delay means comprises set-side logical delay means for delaying the input pulse thereto by a time interval corresponding to an integral multiple of said fundamental period in accordance with an integral part of said set-side added data read out of said memory, and fine delay means for delaying the output pulse from said set-side logical delay means by a time interval shorter than said fundamental period corresponding to a fractional part of said read-out set-side added data; and wherein said reset-side delay means comprises reset-side logical delay means for delaying the input pulse thereto by a time interval corresponding to an integral multiple of said fundamental period in accordance with an integral part of said reset-side added data read out of said memory, and fine delay means for delaying the output pulse from said reset-side logic delay means by a time interval shorter than said fundamental period corresponding to a fractional part of said read-out reset-side added data.
Claim 4
Dependent Claim
236 words
The timing generator of claim 1, further comprising: a memory in which said integral and fractional parts of said timing set data are stored separately and from which they are read out every test cycle, said read-out integral part being provided to said coarse timing generating means; wherein said set-side delay means comprises a set-side adder for adding a fractional part of said read-out set data and said set-side propagation delay variation compensating data, set-side logical delay means for delaying the input pulse thereto by a time interval which is an integral multiple of said fundamental period corresponding to an integral part of said set-side added data, and fine delay means for delaying the output pulse from said set-side logical delay means by a time interval shorter than said fundamental period corresponding to a fractional part of said set-side added data; and wherein said reset-side delay means comprises a reset-side adder for adding a fractional part of said read-out set data and said reset-side propagation delay variation compensating data, reset-side logical delay means for delaying the input pulse thereto by a time interval which is an integral multiple of said fundamental period corresponding to an integral part of said reset-side added data, and fine delay means for delaying the output pulse from said reset-side logical delay means by a time interval shorter than said fundamental period corresponding to a fractional part of said reset-side added data.
Claim 5
Dependent Claim
348 words
A timing generator for IC testers which is provided for each pin of an IC device under test, comprising: a memory which stores an integral part of timing set data expressed in terms of a fundamental period, set-side added data obtained by adding a fractional part of said timing set data and data generated at a post-stage of said timing generator for compensating for set-side propagation delay variations, and a reset-side added data obtained by adding said fractional part of said timing set data and data generated at said post-stage of said timing generator for compensating for reset-side propagation delay variations, said memory being read every test cycle; coarse timing generating means supplied with said integral part of said timing set data read out of said memory, for generating pulses of a period which is an integral multiple of said fundamental period corresponding to said integral part; set-side delay means for delaying the output pulse from said coarse timing generating means by set-side logical delay means by a time interval which is an integral multiple of said fundamental period corresponding to an integral part of said read-out set-side added data and for delaying the output pulse from said set-side logical delay means by fine delay means by a time interval shorter than said fundamental period corresponding to a fractional part of said read-out set-side added data; reset-side delay means for delaying the output pulse from said coarse timing generating means by reset-side logical delay means by a time interval which is an integral multiple of said fundamental period corresponding to an integral part of said read-out reset-side added data and for delaying the output pulse from said reset-side logical delay means by fine delay means by a time interval shorter than said fundamental period corresponding to a fractional part of said read-out reset-side added data, and gate means which permits or inhibits the passage therethrough of the output pulse from said set-side delay means and the output pulse from said reset-side delay means under the control of the set- and reset-side outputs from a waveform generation control circuit.
Claim 6
Dependent Claim
348 words
A timing generator for IC testers which is provided for each pin of an IC device under test, comprising: a memory which stores an integral part of timing set data expressed in terms of a fundamental period, set-side added data obtained by adding a fractional part of said timing set data and data generated at a post-stage of said timing generator for compensating for set-side propagation delay variations, and a reset-side added data obtained by adding said fractional part of said timing set data and data generated at said post-stage of said timing generator for compensating for reset-side propagation delay variations, said memory being read every test cycle; coarse timing generating means supplied with said integral part of said timing set data read out of said memory, for generating pulses of a period which is an integral multiple of said fundamental period corresponding to said integral part; set-side delay means for delaying the output pulse from said coarse timing generating means by set-side logical delay means by a time interval which is an integral multiple of said fundamental period corresponding to an integral part of said read-out set-side added data and for delaying the output pulse from said set-side logical delay means by fine delay means by a time interval shorter than said fundamental period corresponding to a fractional part of said read-out set-side added data; reset-side delay means for delaying the output pulse from said coarse timing generating means by reset-side logical delay means by a time interval which is an integral multiple of said fundamental period corresponding to an integral part of said read-out reset-side added data and for delaying the output pulse from said reset-side logical delay means by fine delay means by a time interval shorter than said fundamental period corresponding to a fractional part of said read-out reset-side added data, and gate means which permits or inhibits the passage therethrough of the output pulse from said set-side delay means and the output pulse from said reset-side delay means under the control of the set- and reset-side outputs from a waveform generation control circuit.
Claim 7
Dependent Claim
129 words
The timing generator of claim 2 or 4, wherein said set-side logical delay means comprises a cascade connection of flip-flops for shift-control of the input pulse thereto by a clock pulse of said fundamental period, and a selector for selectively taking out one of the input to the first-stage of said cascade connection and the outputs from the respective stages thereof in accordance with said set-side added data; and wherein said reset-side logical delay means comprises a cascade connection of flip-flops for shift-control of the input pulse thereto by a clock pulse of said fundamental period, and a selector for selectively taking out one of the input to the first-stage of said cascade connection and the outputs from the respective stages thereof in accordance with said reset-side added data.
Claim 8
Dependent Claim
328 words
A timing generator for IC testers which is provided for each pin of an IC device under test, comprising: a memory in which integral and fractional parts of timing set data expressed in terms of a fundamental period are stored and from which they are read out every test cycle; coarse timing generating means supplied with said integral part of said read-out set data, for generating pulses of a period which is an integral multiple of said fundamental period corresponding to said integral part; set-side delay means which adds together, by a set-side adder, said fractional part of said read-out timing set data and set-side propagation delay variation compensating data generated at a post-stage of said timing generator, delays the output pulse from said coarse timing generating means by set-side logical delay means by a time interval which is an integral multiple of said fundamental period corresponding to an integral part of said added output data, and delays the output pulse from said set-side logical delay means by fine delay means by a time interval corresponding to a fractional part of said added output data; reset-side delay means which adds together, by a reset-side adder, said fractional part of said read-out timing set data and reset-side propagation delay variation compensating data generated at said post-stage of said timing generator, delays the output pulse from said coarse timing generating means by reset-side logical delay means by a time interval which is an integral multiple of said fundamental period corresponding to an integral part of said added output data, and delays the output pulse from said reset-side logical delay means by fine delay means by a time interval corresponding to a fractional part of said added output data; and gate means which is controlled by set- and reset-side outputs from a waveform generation control circuit to permit or inhibit the passage therethrough of the output pulse from said set-side delay means and the output pulse from said reset-side delay means.
Claim 9
Dependent Claim
328 words
A timing generator for IC testers which is provided for each pin of an IC device under test, comprising: a memory in which integral and fractional parts of timing set data expressed in terms of a fundamental period are stored and from which they are read out every test cycle; coarse timing generating means supplied with said integral part of said read-out set data, for generating pulses of a period which is an integral multiple of said fundamental period corresponding to said integral part; set-side delay means which adds together, by a set-side adder, said fractional part of said read-out timing set data and set-side propagation delay variation compensating data generated at a post-stage of said timing generator, delays the output pulse from said coarse timing generating means by set-side logical delay means by a time interval which is an integral multiple of said fundamental period corresponding to an integral part of said added output data, and delays the output pulse from said set-side logical delay means by fine delay means by a time interval corresponding to a fractional part of said added output data; reset-side delay means which adds together, by a reset-side adder, said fractional part of said read-out timing set data and reset-side propagation delay variation compensating data generated at said post-stage of said timing generator, delays the output pulse from said coarse timing generating means by reset-side logical delay means by a time interval which is an integral multiple of said fundamental period corresponding to an integral part of said added output data, and delays the output pulse from said reset-side logical delay means by fine delay means by a time interval corresponding to a fractional part of said added output data; and gate means which is controlled by set- and reset-side outputs from a waveform generation control circuit to permit or inhibit the passage therethrough of the output pulse from said set-side delay means and the output pulse from said reset-side delay means.
Claim 10
Dependent Claim
153 words
The timing generator of claim 3 or 6, wherein said set-side logical delay means comprises a cascade connection of flip-flops for shift-control of the input pulse thereto by a clock pulse of said fundamental period, and a selector for selecting one of the input to the first stage of said cascade connection and outputs from respective stages thereof in accordance with a carry output from said set-side adder and an integral part of said set-side propagation delay variation compensating data; and wherein said reset-side logical delay means comprises a cascade connection of flip-flops for shift-control of the input pulse thereto by a clock pulse of said fundamental period, and a selector for selecting one of the input to the first stage of said cascade connection and outputs from respective stages thereof in accordance with a carry output from said reset-side adder and an integral part of said reset-side propagation delay variation compensating data.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-01-19 | 2001-07-21 | 2002-01-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-01-19 | 2005-07-21 | 2006-01-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-01-19 | 2009-07-21 | 2010-01-20 | $7700.00 | Window Closed / Lapsed |