Abstract A timing generator for generating delay timing signals which have delay time up to n-times of a reference clock period is capable of considerably reducing the hardware size. The timing generator is used in a semiconductor testing apparatus. The timing generator can contribute to reduce the total size and cost of the semiconductor testing apparatus. The timing generator includes a counter for counting the reference clock, an adder for adding the output of the counter to delay data, a series of registers for storing the output of the adder and shifting the output of the adder in synchronism with a delay trigger signal, a series of exclusive OR gates for comparing each output of the registers with the output of the counter and generating coincidence signals when the output from the register and the counter coincide with each other, and an OR gate for receiving the outputs of the exclusive OR gates and generating a signal which is combined of the outputs from the exclusive OR gates.
A timing generator used in a semiconductor testing apparatus for generating delay timing signals which delay up to n-times of a period of a reference clock, comprising: a counter for counting the reference clock: an adder for adding the output of said counter to delay data; a series of registers for storing the output of said adder and shifting said output of said adder in synchronism with a delay trigger signal; a series of exclusive OR gates for comparing each output of said registers with the output of said counter and generating coincidence signals when said output from said register and said counter coincide with each other; and an OR gate for receiving the outputs of said exclusive OR gates and generating a signal which is combined of said outputs from said exclusive OR gates.
Claim 2
Dependent Claim
135 words
A timing generator used in a semiconductor testing apparatus for generating delay timing signals which delay up to n-times of a period of a reference clock, comprising: a counter for counting the reference clock: an adder for adding the output of said counter to delay data; a series of registers for storing the output of said adder and shifting said output of said adder in synchronism with a delay trigger signal; a series of exclusive OR gates for comparing each output of said registers with the output of said counter and generating coincidence signals when said output from said register and said counter coincide with each other; and an OR gate for receiving the outputs of said exclusive OR gates and generating a signal which is combined of said outputs from said exclusive OR gates.