US5095232A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Timing signal delay circuit with high resolution or accuracy
Assignee: Ando Electric Co Ltd
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Filing: 1990-12-10
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Granted: 1992-03-10
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Expires: 2010-12-10
Abstract
Abstract A timing signal delay circuit comprises a counter placed with first delay setting data (21-24) for counting a first clock signal (12) in response to an input timing pulse (11), and a first flip-flop circuit which has a D-input supplied with the output of the counter (1) and a clock input supplied with a second clock signal of the same timing frequency as the first clock signal. For doubling resolution of the delay which the input timing pulse undergoes, there are provided an exclusive-OR gate (4) supplied with a second dealy data signal (31) and a third clock signal (14) of the same timing as the second clock signal (13), an AND gate (5) supplied with the output of the exclusive-OR gate (4) and that of the first flip-flop (3), and a second flip-flop supplied with the output of the AND gate (5) and a fourth clock signal (15) having twice as high frequency as that of the first clock (12). The input timing pulse can be delayed with high resolution or accuracy.
Inventors
- 👤 Kazuhiko Hirano
- 👤 Junichi Saito
- 👤 Takafumi Uehara
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 12:09
CPC Classifications
H; H03; H03K; H03K5/00; H03K5/13; H03K5/131; H03K5/135
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
287 words
A delay circuit for delaying a timing pulse signal by a preset amount, comprising: counter means placed with first delay setting data representing said preset amount of delay and having a timing pulse signal input terminal to which a timing pulse signal to be delayed is applied and a first clock input terminal to which a first clock signal is applied, said counter means counting said first clock signal in response to application of said timing pulse signal until said preset amount of delay has been attained, whereupon said counter means produces an output pulse; a first flip-flop circuit having a first input terminal to which the output pulse of said counter means is applied and a clock input terminal to which a second clock signal having a same frequency as said first clock signal is applied; an exclusive-OR circuit having a first input terminal to which a third clock signal having a same frequency as said second clock signal is applied and a second input terminal to which a second delay setting data signal representing a resolution factor of the delay is applied; an AND circuit having a first input terminal to which the output of said exclusive-OR circuit is applied and a second input terminal to which the output of said first flip-flop circuit is applied; and a second flip-flop circuit having a first input terminal to which the output of said AND circuit is applied, a second input terminal to which a fourth clock signal having twice as high frequency as that of said first clock signal is applied and an output terminal at which an output timing pulse signal delayed relative to said input timing pulse signal by said preset amount is produced.
Claim 2
Dependent Claim
287 words
A delay circuit for delaying a timing pulse signal by a preset amount, comprising: counter means placed with first delay setting data representing said preset amount of delay and having a timing pulse signal input terminal to which a timing pulse signal to be delayed is applied and a first clock input terminal to which a first clock signal is applied, said counter means counting said first clock signal in response to application of said timing pulse signal until said preset amount of delay has been attained, whereupon said counter means produces an output pulse; a first flip-flop circuit having a first input terminal to which the output pulse of said counter means is applied and a clock input terminal to which a second clock signal having a same frequency as said first clock signal is applied; an exclusive-OR circuit having a first input terminal to which a third clock signal having a same frequency as said second clock signal is applied and a second input terminal to which a second delay setting data signal representing a resolution factor of the delay is applied; an AND circuit having a first input terminal to which the output of said exclusive-OR circuit is applied and a second input terminal to which the output of said first flip-flop circuit is applied; and a second flip-flop circuit having a first input terminal to which the output of said AND circuit is applied, a second input terminal to which a fourth clock signal having twice as high frequency as that of said first clock signal is applied and an output terminal at which an output timing pulse signal delayed relative to said input timing pulse signal by said preset amount is produced.
Claim 3
Dependent Claim
83 words
A timing signal delay circuit according to claim 1, wherein said counter means is composed of a counter having a plurality of bit output terminals corresponding to a number of bits of said first delay setting data, and a detection circuit having input terminals connected to said output bit terminals, respectively, for detecting that all bit outputs of said counter assume the same logical value, to thereby output the signal to be applied to the first input terminal of said first flip-flop circuit.
Claim 4
Dependent Claim
29 words
A timing signal delay circuit according to claim 2, wherein said first delay setting data is of four bits while said second delay data signal is of one bit.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-03-10 | 1995-09-09 | 1996-03-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-03-10 | 1999-09-09 | 2000-03-10 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-03-10 | 2003-09-09 | 2004-03-10 | $7700.00 | Window Closed / Lapsed |