Gate spacer to control the base width of a lateral bipolar junction transistor using SOI technology

Claim 1

A lateral bipolar junction transistor structure, in a silicon on insulator layer, on a semiconductor substrate, comprising; field oxide regions in said silicon on insulator layer; a device region between said field oxide regions; a polysilicon structure on said silicon on insulator layer, in center of said device region; insulator sidewall spacers on sides of said polysilicon structure; an emitter region, in said silicon on insulator layer, with an N type dose between about 1E14 and 1E16 atoms/cm 2 , between a first oxide region, and a first insulator sidewall spacer; a heavily doped collector region, in said silicon on insulator layer, with an N type dose between about 1E14 and 1E16 atoms/cm 2 , between a second field oxide region, and a second insulator sidewall spacer; only one lightly doped collector region, in said silicon on insulator layer, with an N type dose between about 1E12 and 1E14 atoms/cm 2 , located under said second insulator sidewall spacer, between said polysilicon gate structure, and said heavily doped collector region, and with no lightly doped collector region under said first insulator sidewall spacer; a base region between said emitter region and said lightly doped collector region, underlying said polysilicon structure; an insulator layer on said heavily doped collector region, on said emitter region, and on said polysilicon gate structure; contact holes in said insulator layer, exposing top surface of said heavily doped collector region, and exposing top surface of said emitter region; and metal contact structures to said emitter region, and to said heavily doped collector region, and to a base region, on said silicon on insulator layer.