Patent US5704058A successfully refreshed from Google Patents.
US5704058A
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Cache bus snoop protocol for optimized multiprocessor computer system
Assignee: International Business Machines Corp
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Filing: 1995-04-21
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Granted: 1997-12-30
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Expires: 2015-04-21
Abstract
Abstract A cache bus snoop protocol optimizes performance of a multiprocessor computer system with multiple level two caches by allocating windows of cache bus snoop activity on a need basis. When a cycle to cacheable address space is requested, the cache bus is granted only after the necessary snoop and write-back cycles are completed. During the snoop and write-back cycles, snoop activity by other devices in inhibited.
Inventors
- 👤 John E. Derrick
- 👤 Christopher M. Herring
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 15:32
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/08; G06F12/0802; G06F12/0806; G06F12/0815; G06F12/0831; G06F12/0811
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
134 words
A method of allocating windows of cache bus bandwidth for cache to cache and system snoop activity on a need basis to minimize impact on performance while maximizing memory page hit accesses comprising the steps of: providing an address space having cacheable and non-cacheable portions; providing a cycle request for access to a selected address within the address space; determining from the selected address if the cycle request requires snoop activity by determining whether the selected address is in the cacheable address space; allowing local bus and expansion bus activity to occur on the cache bus if the cycle request is for non-cacheable address space not requiring snoop activity; and delaying the cycle request if snoop activity is required until it can be determined that the necessary snoop and write-back cycles can be completed.
Claim 2
Independent Claim
134 words
A method of allocating windows of cache bus bandwidth for cache to cache and system snoop activity on a need basis to minimize impact on performance while maximizing memory page hit accesses comprising the steps of: providing an address space having cacheable and non-cacheable portions; providing a cycle request for access to a selected address within the address space; determining from the selected address if the cycle request requires snoop activity by determining whether the selected address is in the cacheable address space; allowing local bus and expansion bus activity to occur on the cache bus if the cycle request is for non-cacheable address space not requiring snoop activity; and delaying the cycle request if snoop activity is required until it can be determined that the necessary snoop and write-back cycles can be completed.
Claim 3
Dependent Claim
24 words
The method of claim 1 further including the step of inhibiting other devices from performing snoop cycles during the necessary snoop and write-back cycles.
Claim 4
Dependent Claim
40 words
The method of claim 2 wherein the step of inhibiting other devices from performing snoop cycles comprises the step of providing a back off signal to the other devices that request a cycle during the necessary snoop and write-back cycles.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-12-29 | 2001-06-30 | 2001-12-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-12-29 | 2005-06-30 | 2005-12-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-12-29 | 2009-06-30 | 2009-12-30 | $7700.00 | Window Closed / Lapsed |