Double-poly monos flash EEPROM cell

Claim 1

A double-poly MONOS EEPROM formed on a semiconductor substrate, said EEPROM comprising: a source formed in said substrate; a drain formed in said substrate; a gate oxide layer formed on said semiconductor substrate adjacent to said source and drain, said gate oxide layer being spaced apart from said drain by a first spacing width, said gate oxide layer being spaced apart from said source by a second spacing width; a select gate formed on said gate oxide layer; a dielectric layer formed on a portion of said select gate, a portion of said drain, and said first spacing width, said second spacing width being exposed by said select gate and said dielectric layer, said dielectric layer used to store carriers, said carriers tunneling into said dielectric layer via said first spacing width in a programming mode, wherein said select gate is used for conserving power in an erase mode; and a control gate formed on said dielectric layer.