Semiconductor integrated circuit

Claim 2

A semiconductor integrated circuit comprising: a rectangular semiconductor chip having a main surface; a plurality of pads formed in a peripheral portion of the main surface of said semiconductor chip, for connection to external connecting members; a plurality of circuit elements of an integrated circuit formed in an area of the main surface other than the peripheral portion in which said plurality of pads are formed; and at least two characteristic evaluating circuit elements including at least one PMOS transistor and at least one NMOS transistor, said at least one PMOS transistor sharing an impurity doped region as a source/drain region with said PMOS transistor of said integrated circuit and said NMOS transistor sharing an impurity doped region as a source/drain region with said NMOS transistor of said integrated circuit, said at least two characteristic evaluating circuit elements being located in an area of the main surface other than the peripheral portion in which said plurality of pads are formed.

Claim 3

A semiconductor integrated circuit according to claim 1, wherein said circuit elements of said integrated circuit include circuit means for electrically isolating said at least two characteristic evaluating circuit elements from said plurality of circuit elements of said integrated circuit at a time of characteristic measurement.

Claim 4

A semiconductor integrated circuit according to claim 1, wherein said at least two characteristic evaluating circuit elements are connected to part of said circuit elements of said integrated circuit so as to be independent from normal operation of the integrated circuit when the integrated circuit effects normal operation.

Claim 5

A semiconductor integrated circuit according to claim 1, wherein said plurality of circuit elements of said integrated circuit include at least one PMOS transistor, and said at least two characteristic evaluating circuit elements include a PMOS transistor sharing an impurity doped region as a source/drain region with said PMOS transistor of said integrated circuit.

Claim 6

A semiconductor integrated circuit according to claim 4, further comprising a first test pad connected to the gate of said PMOS transistor for characteristic evaluating, and at least one second test pad connected to the source/drain region of said PMOS transistor for characteristic evaluating.

Claim 7

A semiconductor integrated circuit according to claim 1, wherein said plurality of circuit elements of said integrated circuit include at least one NMOS transistor, and said at least two characteristic evaluating circuit elements include an NMOS transistor sharing an impurity doped region as a source/drain region with said NMOS transistor of said integrated circuit.

Claim 8

A semiconductor integrated circuit according to claim 6, further comprising a first test pad connected to the gate of said NMOS transistor for characteristic evaluating, and at least one second test pad connected to the source/drain region of said NMOS transistor for characteristic evaluating.

Claim 9

A semiconductor integrated circuit according to claim 1, further comprising a first test pad connected to the gate of said PMOS transistor for characteristic evaluating, at least one second test pad connected to the source/drain region of said PMOS transistor for characteristic evaluating, a third test pad connected to the gate of said NMOS transistor for characteristic evaluating, and at least one fourth test pad connected to the source/drain region of said NMOS transistor for characteristic evaluating.

Claim 10

A semiconductor integrated circuit comprising: a semiconductor substrate having an area in which an integrated circuit is formed; a PMOS transistor of a circuit formed in said semiconductor substrate of the circuit forming area of the integrated circuit having a first source region formed of a first impurity diffusion layer, a first drain region, and a first gate electrode; an NMOS transistor of said circuit formed in said semiconductor substrate of the circuit forming area of the integrated circuit having a second source region formed of a second impurity diffusion layer, a second drain region, and a second gate electrode; a PMOS transistor of a test element sharing said first source region formed of the first impurity diffusion layer with said PMOS transistor of said circuit and having a third drain region and a third gate electrode; and an NMOS transistor of a test element sharing said second source region formed of the second impurity diffusion layer with said NMOS transistor of said circuit and having a fourth drain region and a fourth gate electrode; a first test pad connected to the third gate electrode of said PMOS transistor of said test element; a second test pad connected to the third drain region of said PMOS transistor of said test element; a third test pad connected to the fourth gate electrode of said NMOS transistor of said test element; and a fourth test pad connected to the fourth drain region of said NMOS transistor of said test element; said pMOS and NMOS transistors of said circuit constituting a CMOS inverter circuit which has an input terminal connected to the first and second gate electrodes and an output terminal connected to the first and second drain regions, the first source region commonly used by said PMOS transistor of said test element being connected to the power supply terminal and the second source region commonly used by said NMOS transistor of said test element being connected to reference potential terminal.

Claim 11

A semiconductor integrated circuit comprising: a semiconductor substrate having an area in which an integrated circuit is formed; a PMOS transistor of a circuit formed in said semiconductor substrate of the circuit forming area of the integrated circuit having a first source region formed of a first impurity diffusion layer, a first drain region, and a first gate electrode; an NMOS transistor of said circuit formed in said semiconductor substrate of the circuit forming area of the integrated circuit having a second source region formed of a second impurity diffusion layer, a second drain region, and a second gate electrode; a PMOS transistor of a test element sharing said first source region formed of the first impurity diffusion layer with said PMOS transistor of said circuit and having a third drain region and a third gate electrode; and an NMOS transistor of a test element sharing said second source region formed of the second impurity diffusion layer with said NMOS transistor of said circuit and having a fourth drain region and a fourth gate electrode; a first test pad connected to the third gate electrode of said PMOS transistor of said test element; a second test pad connected to the third drain region of said PMOS transistor of said test element; a third test pad connected to the fourth gate electrode of said NMOS transistor of said test element; and a fourth test pad connected to the fourth drain region of said NMOS transistor of said test element; said pMOS and NMOS transistors of said circuit constituting a CMOS inverter circuit which has an input terminal connected to the first and second gate electrodes and an output terminal connected to the first and second drain regions, the first source region commonly used by said PMOS transistor of said test element being connected to the power supply terminal and the second source region commonly used by said NMOS transistor of said test element being connected to reference potential terminal.

Claim 12

A semiconductor integrated circuit according to claim 9, further comprising: a first load element connected between the third gate electrode of said PMOS transistor of said test element and the power supply terminal; and a second load element connected between the fourth gate electrode of said NMOS transistor of said test element and the reference potential terminal.

Claim 13

A semiconductor integrated circuit according to claim 10, wherein said first and second load elements are resistors.