Logical relocation of memory based on memory device type

Claim 2

In a computer system having a bus coupled to address a plurality of memory units, the bus communicating memory address control signals addressing a predetermined address range, an improvement comprising: logic means for determining at least the fastest of the memory units; and mapping means responsive to the logic means for redirecting the memory address control signals on the bus such that the fastest of the memory units is addressed by addresses at one end of the address range.

Claim 3

The improvement as set forth in claim 1 wherein each of the plurality of memory units comprises one or more memory devices of one of a plurality of memory device types, the memory device types ranging in speed from a fastest memory device type to a slowest memory device type.

Claim 4

The improvement as set forth in claim 2 further including detecting means coupled to the logic means for detecting the memory device type of the memory devices in each of the memory units, the logic means being responsive to the detecting means to determine the fastest of the memory units.

Claim 5

The improvement as set forth in claim 2 wherein the detecting means further determines an access speed of each of the memory units and the logic means determines the fastest of the memory units in response to detecting the memory device type and an access speed of the memory devices in each of the memory units.

Claim 6

The improvement as set forth in claim 2 wherein the memory devices are dynamic random access memories (DRAMs), and wherein the plurality of memory device types includes fast page mode (FP) DRAMs, extended data out (EDO) DRAMs, burst extended data out (BEDO) DRAMs and synchronous DRAMs (SDRAMs).

Claim 7

The improvement as set forth in claim 3 wherein the memory address control signals include a memory unit address control signal for each of the memory units, and wherein the particular memory unit address control signal communicated to each particular memory unit determines an address order of the memory unit with respect to the other memory units in the address range.

Claim 8

The improvement as set forth in claim 6 wherein the mapping means selects the particular memory unit address control signal to direct to a particular memory unit in response to determining the memory device type of each of the memory units, such that the memory units are addressed in order from the fastest of the memory units at one end of the address range to the slowest of the memory units at the opposite end of the address range.

Claim 9

The improvement as set forth in claim 3 further including a set of registers coupled to the mapping means, the set of registers including one register for each of the memory units, each register storing a starting address of a corresponding memory unit, the starting address stored in the register determining an order of the memory unit with respect to the other memory units in the address range.

Claim 10

The improvement as set forth in claim 8 further including logic means for determining a storage capacity of each of the memory units, wherein the starting address stored in each register for each of the memory units is determined in response to the memory unit device type and storage capacity of each memory unit, such that the memory units are addressed in order from the fastest of the memory units at one end of the address range to the slowest of the memory units at the opposite end of the address range.

Claim 11

The improvement as set forth in claim 9 wherein the memory address control signals control addressing of the memory in response to the starting address stored in the registers.

Claim 12

The improvement as set forth in claim 6 wherein each of the memory units is addressed as a memory row and the memory unit address control signals are memory row address control signals.

Claim 13

A circuit for optimizing memory subsystem performance in a computer system, the memory subsystem including a bus communicating memory address control signals to a plurality of memory units in a predetermined address range, the memory units ranging in performance from a highest performance memory unit to a lowest performance memory unit, the circuit comprising: memory type detection logic for identifying at least the highest performance memory unit; and signal mapping logic responsive to the memory type detection logic for controlling the memory address control signals to logically relocate the highest performance memory unit to one end of the address range, independent of a physical location of the memory unit in the memory subsystem.

Claim 14

A circuit for optimizing memory subsystem performance in a computer system, the memory subsystem including a bus communicating memory address control signals to a plurality of memory units in a predetermined address range, the memory units ranging in performance from a highest performance memory unit to a lowest performance memory unit, the circuit comprising: memory type detection logic for identifying at least the highest performance memory unit; and signal mapping logic responsive to the memory type detection logic for controlling the memory address control signals to logically relocate the highest performance memory unit to one end of the address range, independent of a physical location of the memory unit in the memory subsystem.

Claim 15

The circuit as set forth in claim 12 wherein each of the plurality of memory units comprises one or more memory devices of one of a plurality of memory device types, the memory device types ranging from a highest performance memory device type to a lowest performance memory device type.

Claim 16

The circuit as set forth in claim 13 wherein the memory type detection logic identifies the highest performance memory unit in response to detecting the memory device type of the memory devices in each of the memory units.

Claim 17

The circuit as set forth in claim 13 wherein the memory type detection logic identifies the highest performance memory unit in response to detecting the memory device type and an access speed of the memory devices in each of the memory units.

Claim 18

The circuit as set forth in claim 15 wherein the memory devices are dynamic random access memories (DRAMs) and wherein the plurality of memory device types includes fast page mode (FP) DRAMs, extended data out (EDO) DRAMs, burst extended data out (BEDO) DRAMs and synchronous DRAMs (SDRAMs).

Claim 19

The circuit as set forth in claim 14 wherein the memory address control signals include a memory unit address control signal for each of the memory units, and wherein the particular memory unit address control signal communicated to each particular memory unit determines a logical location of the memory unit with respect to the other memory units in the address range.

Claim 20

The circuit as set forth in claim 17 wherein the signal mapping logic selects a particular memory unit address control signal to direct to a particular memory unit in response to determining the memory device type of each of the memory units, such that the memory units are logically ordered from the highest performance memory unit at one end of the address range to the lowest performance memory unit at the opposite end of the address range.

Claim 21

The circuit as set forth in claim 15 further including a set of registers coupled to the signal mapping logic, the set of registers including a register for each of the memory units, each register storing a starting address of a corresponding memory unit, the starting address stored in the register determining a logical order of the memory unit with respect to the other memory units in the address range.

Claim 22

The circuit as set forth in claim 19 further including memory size detection logic for determining a storage capacity of each of the memory units and wherein the starting address stored in each register for each of the memory units is determined in response to the memory unit device type and storage capacity of each memory unit, such that the memory units are addressed in order from the fastest of the memory units at one end of the address range to the slowest of the memory units at the opposite end of the address range.

Claim 23

The circuit as set forth in claim 20 wherein the memory address control signals control addressing of the memory response to the starting address stored in the registers.

Claim 24

The circuit as set forth in claim 17 wherein each of the memory units is addressed as a memory row and the memory unit address control signals are memory row address control signals.

Claim 25

A computer system comprising: a processor; a bus coupled to the processor for communicating information; a main memory coupled to the bus, the main memory having a predetermined address range, the main memory including a plurality of memory units ranging in performance from a highest performance memory unit to a lowest performance memory unit; and a memory controller for controlling accesses to the main memory, the memory controller including: a plurality of signal lines for communicating memory address control signals, memory type detection logic for identifying at least the highest performance memory unit, and memory unit mapping logic responsive to the memory type detection logic for controlling the memory address control signals to logically relocate the highest performance memory unit to one end of the address range, independent of a physical location of the memory unit in the memory subsystem.

Claim 26

A computer system comprising: a processor; a bus coupled to the processor for communicating information; a main memory coupled to the bus, the main memory having a predetermined address range, the main memory including a plurality of memory units ranging in performance from a highest performance memory unit to a lowest performance memory unit; and a memory controller for controlling accesses to the main memory, the memory controller including: a plurality of signal lines for communicating memory address control signals, memory type detection logic for identifying at least the highest performance memory unit, and memory unit mapping logic responsive to the memory type detection logic for controlling the memory address control signals to logically relocate the highest performance memory unit to one end of the address range, independent of a physical location of the memory unit in the memory subsystem.

Claim 27

The computer system as set forth in claim 23 wherein each of the plurality of memory units comprises one or more memory devices of one of a plurality of memory device types, the memory device types ranging from a highest performance memory device type to a lowest performance memory device type.

Claim 28

The computer system as set forth in claim 24 wherein the memory type detection logic identifies the highest performance memory unit in response to detecting the memory device type of the memory devices in each of the memory units.

Claim 29

The computer system as set forth in claim 25 further including a basic input output system (BIOS) having memory type detection code and wherein the memory type detection logic is responsive to the BIOS to detect the memory device type of the memory devices in each of the memory units.

Claim 30

The computer system as set forth in claim 24 wherein the memory type detection logic identifies the highest performance memory unit in response to detecting the memory device type and an access speed of the memory devices in each of the memory units.

Claim 31

The computer system as set forth in claim 24 wherein the memory devices are dynamic random access memories (DRAMs) and wherein the plurality of memory device types includes fast page mode (FP) DRAMs, extended data out (EDO) DRAMs, burst extended data out (BEDO) DRAMs and synchronous DRAMs (SDRAMs).

Claim 32

The computer system as set forth in claim 25 wherein the memory address control signals include a memory unit address control signal for each of the memory units, and wherein the particular memory unit address control signal communicated to each particular memory unit determines a logical location of the memory unit with respect to the other memory units in the address range.

Claim 33

The computer system as set forth in claim 29 wherein the memory unit mapping logic selects a particular memory unit address control signal to direct to a particular memory unit in response to determining the memory device type of each of the memory units, such that the memory units are logically ordered from the highest performance memory unit at one end of the address range to the lowest performance memory unit at the opposite end of the address range.

Claim 34

The computer system as set forth in claim 25 further including a set of registers coupled to the memory unit mapping logic, the set of registers including a register for each of the memory units, each register storing a starting address of a corresponding memory unit, the starting address stored in the register determining a logical order of the memory unit with respect to the other memory units in the address range.

Claim 35

The computer system as set forth in claim 31 further including memory size detection logic for determining a storage capacity of each of the memory units and wherein the starting address stored in each register for each of the memory units is determined in response to the memory unit device type and storage capacity of each memory unit, such that the memory units are addressed in order from the fastest of the memory units at one end of the address range to the slowest of the memory units at the opposite end of the address range.

Claim 36

The computer system as set forth in claim 32 wherein the memory address control signals control addressing of the memory in response to the starting address stored in the registers.

Claim 37

The computer system as set forth in claim 29 wherein each of the memory units is addressed as a memory row and the memory unit address control signals are memory row address control signals.

Claim 38

In a computer system, a method for optimizing memory subsystem performance, the memory subsystem including a plurality of memory units in a predetermined address range, the memory units ranging in performance from a highest performance memory unit to a lowest performance memory unit, the method comprising the steps of: identifying at least the highest performance unit; and logically relocating the highest performance memory unit to one end of the address range, independent of a physical location of the memory unit in the memory subsystem.

Claim 39

In a computer system, a method for optimizing memory subsystem performance, the memory subsystem including a plurality of memory units in a predetermined address range, the memory units ranging in performance from a highest performance memory unit to a lowest performance memory unit, the method comprising the steps of: identifying at least the highest performance unit; and logically relocating the highest performance memory unit to one end of the address range, independent of a physical location of the memory unit in the memory subsystem.

Claim 40

The method as set forth in claim 35 wherein each of the plurality of memory units comprises one or more memory devices of one of a plurality of memory device types, the memory device types ranging from a highest performance memory device type to a lowest performance memory device type.

Claim 41

The method as set forth in claim 36 further including a step of detecting the memory device type of the memory devices in each of the memory units.

Claim 42

The method as set forth in claim 37 wherein the step of identifying is performed in response to detecting the memory device type.

Claim 43

The method as set forth in claim 38 further including a step of logically relocating the remaining memory units in performance order such that the lowest performance memory unit is logically located at an end of the address range opposite the highest performance memory unit.

Claim 44

The method as set forth in claim 38 further including a step of determining the access speed of the memory devices in each of the memory units, and wherein the step of identifying is performed in response to detecting the device type and determining the access speed.

Claim 45

The method as set forth in claim 39 wherein the plurality of memory device types includes fast page mode (FP) DRAMs, extended data out (EDO) DRAMs, burst extended data out (BEDO) DRAMs and synchronous DRAMs (SDRAMs).

Claim 46

The method as set forth in claim 39 wherein the computer system includes a memory bus communicating memory address control signals to the memory units, the memory address control signals identifying a particular memory addressing order, and wherein the step of logically relocating is performed by remapping the memory address control signals on the memory bus.

Claim 47

The method as set forth in claim 39 wherein the computer system includes a set of registers, the set of registers including one register for each of the memory units, each register storing a starting address of the corresponding memory unit, and wherein the steps of logically relocating are performed by changing the starting addresses of the memory units in the registers.