Semiconductor integrated circuit device and fabrication method therefor

Claim 2

A semiconductor integrated circuit device comprising an insulating layer covering a semiconductor substrate, a resistor layer comprising a first polysilicon layer formed on said insulating layer, a protection insulation film formed on said resistor layer, a capacitor comprising a lower electrode constituted by a second polysilicon layer and formed on said insulating layer, a dielectric film formed on said lower electrode and an upper electrode constituted by a third polysilicon layer formed on said dielectric film, and a transistor portion comprising a gate electrode constituted by a fourth polysilicon layer overlying said semiconductor substrate, wherein said first and second polysilicon layers are simultaneously formed and have equal sheet resistance, and wherein said third and fourth polysilicon layers are simultaneously formed and have equal sheet resistance.

Claim 3

The device as claimed in claim 1, wherein said stacked-layer structure is composed of a lower silicon oxide film, an intermediate silicon nitride film formed on said lower silicon oxide film and an upper silicon oxide film formed on said silicon nitride film.

Claim 4

The device as claimed in claim 1, wherein said first polysilicon layer and said second polysilicon layer have the same film thickness and the same impurity concentration to provide the same sheet resistance.

Claim 5

The device as claimed in claim 1, further comprising an insulated-gate field-effect transistor having a gate electrode, said gate electrode has the same construction as said upper electrode.

Claim 6

The device as claimed in claim 4, wherein each of said gate electrode and the upper electrode is a polycide structure in which a silicide film is formed on a polysilicon layer.

Claim 7

A semiconductor integrated circuit device comprising: a semiconductor substrate; an insulating layer covering said semiconductor substrate; a capacitor including a lower electrode having a first portion and a second portion, each of said first and second portions of said lower electrode being formed on said insulating layer, a dielectric film having a third portion and a fourth portion, each of said third and fourth portions being respectively formed on said first and second portions of said lower electrode, and an upper electrode formed on said third portion of said dielectric film; an interlayer insulating film covering said upper electrode and said fourth portion of said dielectric film; a plurality of contact holes selectively formed in said interlayer insulating film and said fourth portion of said dielectric film along one side of said upper electrode to expose a plurality of parts of said second portion of said lower electrode; a conductive layer filling each of said contact holes, said contact holes being in contact with each of said parts of said second portion of said lower electrode; and an insulated-gate field-effect transistor having a gate electrode, said gate electrode being formed simultaneously with and having a same sheet resistance as said upper electrode.

Claim 8

A semiconductor integrated circuit device comprising: a semiconductor substrate; an insulating layer covering said semiconductor substrate; a capacitor including a lower electrode having a first portion and a second portion, each of said first and second portions of said lower electrode being formed on said insulating layer, a dielectric film having a third portion and a fourth portion, each of said third and fourth portions being respectively formed on said first and second portions of said lower electrode, and an upper electrode formed on said third portion of said dielectric film; an interlayer insulating film covering said upper electrode and said fourth portion of said dielectric film; a plurality of contact holes selectively formed in said interlayer insulating film and said fourth portion of said dielectric film along one side of said upper electrode to expose a plurality of parts of said second portion of said lower electrode; a conductive layer filling each of said contact holes, said contact holes being in contact with each of said parts of said second portion of said lower electrode; and an insulated-gate field-effect transistor having a gate electrode, said gate electrode being formed simultaneously with and having a same sheet resistance as said upper electrode.

Claim 9

The device as claimed in claim 6, wherein said dielectric film includes a stacked-layer structure of a first silicon oxide film formed on said lower electrode, a silicon nitride film formed on said first silicon oxide film and a second silicon oxide film formed on said silicon nitride film, and said device further comprises a protective insulation film covering said resistor layer, said protective insulating film having said stacked-layer structure.

Claim 10

The device as claimed in claim 6, wherein each of said gate electrode and said upper electrode is a polycide structure in which a silicide film is formed on a polysilicon layer.