Patent US5699303A successfully refreshed from Google Patents.
US5699303A
Expired / Lapsed
US
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Semiconductor memory device having controllable supplying capability of internal voltage
Assignee: Mitsubishi Electric Corp
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Filing: 1996-05-13
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Granted: 1997-12-16
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Expires: 2016-05-13
Abstract
Abstract When an external RAS and external CAS are input to a RAS buffer and a CAS buffer, an internal RAS and an internal CAS are generated. The internal RAS is input to a clock generating circuit and a CBR mode determination circuit and the internal CAS is input to the CBR mode determination circuit. The clock generating circuit outputs a pump clock to first and second WL pumps upon input of internal RAS, and the first WL pump supplies charge to a Vpp power supply. If CAS is input prior to RAS during refresh operation, CBR mode determination circuit inputs a CBR mode signal to the second WL pump which supplies charge to Vpp power supply together with the first WL pump when the pump clock and the CBR mode signal is input thereto.
Inventors
- 👤 Takeshi Hamamoto
- 👤 Kiyohiro Furutani
- 👤 Yoshikazu Morooka
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 15:27
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C11/408; G11C11/4085; G11C11/406; G11C11/4074; G11C5/00; G11C5/14; G11C5/145; G11C5/146
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
188 words
A semiconductor memory device, comprising: a plurality of memory blocks each including a plurality of memory cells arranged in a matrix of rows and columns; mode signal generating means responsive to an external control signal for generating a mode signal selectively indicating a first mode and a second mode different from the first mode; divided operating means responsive to said mode signal for operating a first number of memory blocks among said plurality of memory blocks when said mode signal indicates the first mode and for operating a second number of memory blocks when said mode signal indicates said second mode, the second number being larger than said first number; and internal voltage generating means for generating an internal voltage based on an external power supply voltage to supply said internal voltage to a memory block in operation due to said divided operating means among said plurality of memory blocks, said internal voltage generating means being responsive to said mode signal and having a first supplying capability when at said first mode and a second supplying capability larger than said first supplying capability when at said second mode.
Claim 2
Dependent Claim
188 words
A semiconductor memory device, comprising: a plurality of memory blocks each including a plurality of memory cells arranged in a matrix of rows and columns; mode signal generating means responsive to an external control signal for generating a mode signal selectively indicating a first mode and a second mode different from the first mode; divided operating means responsive to said mode signal for operating a first number of memory blocks among said plurality of memory blocks when said mode signal indicates the first mode and for operating a second number of memory blocks when said mode signal indicates said second mode, the second number being larger than said first number; and internal voltage generating means for generating an internal voltage based on an external power supply voltage to supply said internal voltage to a memory block in operation due to said divided operating means among said plurality of memory blocks, said internal voltage generating means being responsive to said mode signal and having a first supplying capability when at said first mode and a second supplying capability larger than said first supplying capability when at said second mode.
Claim 3
Dependent Claim
101 words
The semiconductor memory device according to claim 1, wherein said internal voltage generating means includes first voltage generating means for generating an internal voltage to be supplied to said memory blocks in operation due to said divided operating means regardless of the state of said mode signal; and second voltage generating means inactivated when said mode signal indicates said first mode and activated when said mode signal indicates said second mode for generating an internal voltage to be supplied to said second number of memory blocks in operation due to said divided operating means together with said first voltage generating means.
Claim 4
Dependent Claim
36 words
The semiconductor memory device according to claim 2, wherein said internal voltage generating means further includes clock signal generating means for generating a clock signal to be applied to said first and second voltage generating means.
Claim 5
Dependent Claim
107 words
The semiconductor memory device according to claim 1, wherein said internal voltage generating means includes first and third voltage generating means for generating an internal voltage to be supplied to said memory blocks in operation due to said divided operating means regardless of the state of said mode signal; and second and fourth voltage generating means inactivated when said mode signal indicates said first mode and activated when said mode signal indicates said second mode for generating an internal voltage to be supplied to said second number of memory blocks in operation due to said divided operating means together with said first and third voltage generating means.
Claim 6
Dependent Claim
61 words
The semiconductor memory device according to claim 4, wherein said internal voltage generating means further includes first clock signal generating means for generating a first clock signal to be applied to said first and second voltage generating means; and second clock signal generating means for generating a second clock signal to be applied to said third and fourth voltage generating means.
Claim 7
Dependent Claim
232 words
The semiconductor memory device according to claim 1, wherein each of said memory blocks includes a first function circuit and a second function circuit different from said first function circuit; and said internal voltage generating means includes first voltage generating means for generating a first internal voltage to be supplied to said first function circuit of said memory block in operation due to said divided operating means regardless of the state of said mode signal; second voltage generating means inactivated when said mode signal indicates said first mode and activated when said mode signal indicates said second mode for generating a second internal voltage generally equal to the first internal voltage to be supplied to said first function circuits of said second number of memory blocks in operation due to said divided operating means; third voltage generating means for generating a third internal voltage to be supplied to said second function circuit of said memory block in operation due to said divided operating means regardless of the state of said mode signal; and fourth voltage generating means inactivated when said mode signal indicates said first mode and activated when said mode signal indicates said second mode for generating a fourth internal voltage generally equal to the third internal voltage to be supplied to said second function circuits of said second number of memory blocks in operation due to said divided operating means.
Claim 8
Dependent Claim
68 words
The semiconductor memory device according to claim 1, wherein said external control signal includes row address strobe signal and column address strobe signal; and said mode signal indicates said first mode when said column address strobe signal is input after input of said row address strobe signal and indicates said second mode when said column address strobe signal is input before input of said row address strobe signal.
Claim 9
Dependent Claim
25 words
The semiconductor memory device according to claim 1, wherein said internal voltage is a boosted power supply voltage higher than said external power supply voltage.
Claim 10
Dependent Claim
21 words
The semiconductor memory device according to claim 1, wherein said internal voltage is a substrate voltage lower than the ground voltage.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-12-15 | 2001-06-16 | 2001-12-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-12-15 | 2005-06-16 | 2005-12-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-12-15 | 2009-06-16 | 2009-12-16 | $7700.00 | Window Closed / Lapsed |