US5587956A
Expired / Lapsed
US
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Semiconductor memory device having function of generating boosted potential
Assignee: Mitsubishi Electric Corp
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Filing: 1995-08-17
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Granted: 1996-12-24
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Expires: 2015-08-17
Abstract
Abstract A level determining circuit performs level determination of a potential of a boosted potential node. A determination control circuit is provided for controlling a level determination timing of the level determining circuit. The determination control circuit supplies a control pulse signal of a long cycle to the level determining circuit when a charge pump is not operating, and supplies the control pulse signal of a short cycle to the level determining circuit when the charge pump is operating. The level determining circuit performs the level determination in accordance with a timing defined by the control pulse signal supplied from the determination control circuit. In response to the result of determination, the charge pump is driven. In this manner, a power consumption of a semiconductor memory device can be reduced, and overshoot of a boosted potential of the semiconductor memory device can be prevented.
Inventors
- 👤 Susumu Tanida
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 15:39
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C8/00; G11C8/08; G11C5/00; G11C5/14; G11C5/145
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
252 words
A semiconductor memory device comprising: a boosted potential node provided for outputting a boosted potential; determination cycle control means for outputting a control pulse signal having a controllable cycle for defining a cycle used for determining a level of the potential of said boosted potential node; level determining means for comparing the potential of said boosted potential node with a predetermined reference potential to determine a relative level of the potential of said boosted potential node with respect to the reference potential in accordance with a determination cycle defined by said control pulse signal output from said determination cycle control means; drive pulse oscillating means for oscillating a drive pulse signal when said level determining means determines that the potential of said boosted potential node is lower than said reference potential; and charge pump means for being driven to supply an electric charge for raising the potential of said boosted potential node to said boosted potential node in response to the drive pulse signal output from said drive pulse oscillating means, wherein said determination cycle control means outputs a control pulse signal of a first cycle in response to the determination by said level determining means that the potential of said boosted potential node is equal to or higher than said reference potential, and outputs the control pulse signal of a second cycle shorter than said first cycle in response to the determination by said level determining means that the potential of said boosted potential node is lower than said reference potential.
Claim 2
Dependent Claim
252 words
A semiconductor memory device comprising: a boosted potential node provided for outputting a boosted potential; determination cycle control means for outputting a control pulse signal having a controllable cycle for defining a cycle used for determining a level of the potential of said boosted potential node; level determining means for comparing the potential of said boosted potential node with a predetermined reference potential to determine a relative level of the potential of said boosted potential node with respect to the reference potential in accordance with a determination cycle defined by said control pulse signal output from said determination cycle control means; drive pulse oscillating means for oscillating a drive pulse signal when said level determining means determines that the potential of said boosted potential node is lower than said reference potential; and charge pump means for being driven to supply an electric charge for raising the potential of said boosted potential node to said boosted potential node in response to the drive pulse signal output from said drive pulse oscillating means, wherein said determination cycle control means outputs a control pulse signal of a first cycle in response to the determination by said level determining means that the potential of said boosted potential node is equal to or higher than said reference potential, and outputs the control pulse signal of a second cycle shorter than said first cycle in response to the determination by said level determining means that the potential of said boosted potential node is lower than said reference potential.
Claim 3
Dependent Claim
138 words
The semiconductor memory device according to claim 1, further comprising reference pulse oscillating means for oscillating a reference pulse signal to set said first cycle, wherein said determination cycle control means receives said reference pulse signal and said drive pulse signal, and operates to output, as the control pulse signal of said first cycle, a signal of the same cycle as said reference pulse signal in response to the determination by said level determining means that the potential of said boosted potential node is equal to or higher than said reference potential, and output, as the control pulse signal of said second cycle, a signal of the same cycle as said drive pulse signal in response to the determination by said level determining means that the potential of said boosted potential node is lower than said reference potential.
Claim 4
Dependent Claim
136 words
The semiconductor memory device according to claim 2, wherein said level determining means outputs a signal attaining a first level when the potential of said boosted potential node is equal to or higher than said reference potential and attaining a second level when the potential of said boosted potential node is lower than said reference potential; and said determination cycle control means includes: first gate means for receiving said reference pulse signal and the output signal of said level determining means, and outputting said reference pulse signal when the output signal of said level determining means is at said first level, and second gate means for receiving the output signal of said first gate means and said drive pulse signal, and outputting, as said control pulse signal, a signal indicative of OR of the received signals.
Claim 5
Dependent Claim
57 words
The semiconductor memory device according to claim 3, wherein said first gate means includes: inverter means for inverting and outputting the output signal of said level determining means; and logical gate means for receiving the output signal of said inverter means and said reference pulse signal, and outputting a signal indicative of AND of the received signals.
Claim 6
Dependent Claim
102 words
The semiconductor memory device according to claim 3, wherein said level determining means includes: first latch means being responsive to said control pulse signal to generate and hold a potential at said first level when the potential of said boosted potential node is equal to or higher than said reference potential, and to generate and hold a potential at said second level when the potential of said boosted potential node is lower than said reference potential; and second latch means being responsive to said control pulse signal to output the potential generated by said first latch means and hold the output state.
Claim 7
Dependent Claim
61 words
The semiconductor memory device according to claim 2, wherein said reference pulse oscillating means includes odd first inverter means for defining said first cycle, said drive pulse oscillating means includes odd second inverter means being operable as inverters for defining said second cycle, and the number of said first inverter means is larger than the number of said second inverter means.
References Cited (Backward Citations)
US5406523A
Cited
US5361237A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-12-24 | 2000-06-24 | 2000-12-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-12-24 | 2004-06-24 | 2004-12-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-12-24 | 2008-06-24 | 2008-12-24 | $7700.00 | Window Closed / Lapsed |