Patent US5699234A successfully refreshed from Google Patents.
US5699234A
Expired / Lapsed
US
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Stacking of three dimensional high density interconnect modules with metal edge contacts
Assignee: General Electric Co
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Filing: 1997-01-28
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Granted: 1997-12-16
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Expires: 2017-01-28
Abstract
Abstract A method for fabricating a stack of circuit modules includes providing a plurality of substrates having module interconnection layers. Each of the substrates has a circuit chip with chip pads positioned therein and an electrically conductive feed-through line extending from a first surface of the substrate to a second surface of the substrate with the first surface being perpendicular to the second surface. Each of the module interconnection layers is situated over a respective first surface of each of the substrates and includes a module dielectric layer having module vias therein and a module pattern of electrical conductors extending through the module vias to couple the selected chip pads to the feed-through line. The plurality of substrates are stacked. A side interconnection layer is applied over a side surface including the second surfaces of the substrates. The side interconnection layer includes a side dielectric layer having side vias therein aligned with predetermined ones of the feed-through lines and a side pattern of electrical conductors extending through the side vias.
Inventors
- 👤 Richard Joseph Saia
- 👤 Bernard Gorowitz
- 👤 Kevin Matthew Durocher
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 21:45
CPC Classifications
H; H10; H10W; H10W90/00; H05; H05K; H05K1/00; H05K1/02; H05K1/14; H05K1/144; H05K3/00; H05K3/40; H05K3/403; H10W70/00; H10W70/099; H10W70/60; H10W70/611; H10W70/614; H05K1/03; H05K1/0306; H05K2201/00; H05K2201/09; H05K2201/09209; H05K2201/095; H05K2201/09581; H05K3/46; H05K3/4611; H05K3/4626; H05K3/4629; H05K3/4685; H10W72/00; H10W72/071; H10W72/073; H10W72/07331; H10W72/30; H10W72/351; H10W72/353; H10W72/354; H10W72/834; H10W90/701; H10W90/721; H10W90/722; Y; Y10; Y10T; Y10T29/00; Y10T29/49; Y10T29/49002; Y10T29/49117; Y10T29/49124; Y10T29/49126
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
158 words
A stack of two dimensional circuit modules, comprising: a plurality of substrates in stacked configuration, each of the substrates having a circuit chip with chip pads positioned therein and each of the substrates having an electrically conductive feed-through line extending from a first surface of the substrate to a second surface of the substrate, the first surface being perpendicular to the second surface; a module interconnection layer over a respective first surface of each of the substrates, the interconnection layer comprising a module dielectric layer having module vias therein aligned with at least one of the chip pads and the feed-through line and a module pattern of electrical conductors extending through the module vias; a side interconnection layer over the second surfaces of the substrates, the side interconnection layer comprising a side dielectric layer having side vias therein aligned with predetermined ones of the feed-through lines and a side pattern of electrical conductors extending through the side vias.
Claim 2
Dependent Claim
158 words
A stack of two dimensional circuit modules, comprising: a plurality of substrates in stacked configuration, each of the substrates having a circuit chip with chip pads positioned therein and each of the substrates having an electrically conductive feed-through line extending from a first surface of the substrate to a second surface of the substrate, the first surface being perpendicular to the second surface; a module interconnection layer over a respective first surface of each of the substrates, the interconnection layer comprising a module dielectric layer having module vias therein aligned with at least one of the chip pads and the feed-through line and a module pattern of electrical conductors extending through the module vias; a side interconnection layer over the second surfaces of the substrates, the side interconnection layer comprising a side dielectric layer having side vias therein aligned with predetermined ones of the feed-through lines and a side pattern of electrical conductors extending through the side vias.
Claim 3
Dependent Claim
15 words
The stack of claim 1, further comprising a passivation layer over the side interconnection layer.
Claim 4
Dependent Claim
15 words
The stack of claim 1, wherein at least some of the substrates comprise ceramic material.
Claim 5
Dependent Claim
200 words
A stack of two dimensional circuit modules, comprising: a plurality of substrates in stacked configuration, each of the substrates having a circuit chip with chip pads positioned therein and each of the substrates having an electrically conductive feed-through line extending from a first surface of the substrate to a second surface of the substrate, the first surface being perpendicular to the second surface; a base metallization layer patterned over at least a portion of the first surface of each of the substrates, the base metallization layer being electrically coupled to the feed-through line; a module interconnection layer over a respective base metallization layer and a respective first surface of each of the substrates, the interconnection layer comprising a module dielectric layer having module vias therein aligned with at least one of the chip pads and at least a portion of the base metallization layer, and a module pattern of electrical conductors extending through the module vias; a side interconnection layer over the second surfaces of the substrates, the side interconnection layer comprising a side dielectric layer having side vias therein aligned with predetermined ones of the feed-through lines and a side pattern of electrical conductors extending through the side vias.
Claim 6
Dependent Claim
200 words
A stack of two dimensional circuit modules, comprising: a plurality of substrates in stacked configuration, each of the substrates having a circuit chip with chip pads positioned therein and each of the substrates having an electrically conductive feed-through line extending from a first surface of the substrate to a second surface of the substrate, the first surface being perpendicular to the second surface; a base metallization layer patterned over at least a portion of the first surface of each of the substrates, the base metallization layer being electrically coupled to the feed-through line; a module interconnection layer over a respective base metallization layer and a respective first surface of each of the substrates, the interconnection layer comprising a module dielectric layer having module vias therein aligned with at least one of the chip pads and at least a portion of the base metallization layer, and a module pattern of electrical conductors extending through the module vias; a side interconnection layer over the second surfaces of the substrates, the side interconnection layer comprising a side dielectric layer having side vias therein aligned with predetermined ones of the feed-through lines and a side pattern of electrical conductors extending through the side vias.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-12-15 | 2001-06-16 | 2001-12-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-12-15 | 2005-06-16 | 2005-12-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-12-15 | 2009-06-16 | 2009-12-16 | $7700.00 | Window Closed / Lapsed |