US5696951A
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US
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Signal deskewing system for synchronous logic circuit
Assignee: Credence Systems Corp
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Filing: 1996-01-03
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Granted: 1997-12-09
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Expires: 2016-01-03
Abstract
Abstract A global clock signal is distributed from its source to each module of a distributed synchronous logic circuit via two separate transmission lines. Portions of the two transmission lines extending between the clock signal source and each module are of similar length but have dissimilar velocities of signal propagation. A resulting phase difference between corresponding pulses of the global clock signal arriving at each module via the two transmission lines is proportional to the length of the transmission lines, and is therefore proportional to the inherent clock signal delay in either transmission line. A deskewing circuit at each module further delays the global clock signal after it arrives at the module on a first of the two transmission lines to produce a local clock signal at the module. The deskewing circuit at each module detects the phase difference between global clock signal pulses arriving at the module on the two transmission lines to determine the inherent delay of the first transmission line and then adjusts the local clock delay so that the sum of the inherent delay and local clock delay equals a standard delay. With the standard delay the same for all modules, the local clock signals produced at all modules are in phase with one another.
Inventors
- 👤 Charles A. Miller
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 08:36
CPC Classifications
G; G06; G06F; G06F1/00; G06F1/04; G06F1/12; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/319; G01R31/31917; G01R31/31922; G06F1/10; G01R31/31903; G01R31/31908; G01R31/3191
Claims Analysis
Total Claims: 35
Claim 1
Independent Claim
137 words
A method for producing a separate local clock signal at each of a plurality of modules of a distributed synchronous logic circuit in response to a global clock signal generated by a clock signal source, wherein the local clock signals are substantially in phase with one another, the method comprising the steps of: continuously conveying the global clock signal from said clock signal source to each module via a transmission line while concurrently sensing a length of said transmission line between said clock signal source and each module; and delaying said global clock signal as it arrives at each module via said transmission line by a delay time that is a function of the sensed transmission line length between the clock signal source and the module, thereby to produce a separate local clock signal at each module.
Claim 2
Independent Claim
137 words
A method for producing a separate local clock signal at each of a plurality of modules of a distributed synchronous logic circuit in response to a global clock signal generated by a clock signal source, wherein the local clock signals are substantially in phase with one another, the method comprising the steps of: continuously conveying the global clock signal from said clock signal source to each module via a transmission line while concurrently sensing a length of said transmission line between said clock signal source and each module; and delaying said global clock signal as it arrives at each module via said transmission line by a delay time that is a function of the sensed transmission line length between the clock signal source and the module, thereby to produce a separate local clock signal at each module.
Claim 3
Dependent Claim
20 words
The method in accordance with claim 1 wherein said delay time is inversely related to the sensed transmission line length.
Claim 4
Independent Claim
173 words
A method for producing a separate local clock signal at each of a plurality of modules of a distributed synchronous logic system in response to a global clock signal generated by a clock signal source, wherein the local clock signals are substantially in phase with one another, the method comprising the steps of: conveying the global clock signal from said clock signal source to each module via each of first and second transmission lines, the first and second transmission lines being of substantially equal length between the clock signal source and each module but having substantially dissimilar velocities of signal propagation; sensing a length of said first and second transmission lines between said clock signal source and each module; and delaying said global clock signal as it arrives at each module on one of said first and second transmission lines by a delay time that is a function of the sensed transmission line length between that module and said clock signal source, thereby to produce a separate local clock signal at each module.
Claim 5
Independent Claim
173 words
A method for producing a separate local clock signal at each of a plurality of modules of a distributed synchronous logic system in response to a global clock signal generated by a clock signal source, wherein the local clock signals are substantially in phase with one another, the method comprising the steps of: conveying the global clock signal from said clock signal source to each module via each of first and second transmission lines, the first and second transmission lines being of substantially equal length between the clock signal source and each module but having substantially dissimilar velocities of signal propagation; sensing a length of said first and second transmission lines between said clock signal source and each module; and delaying said global clock signal as it arrives at each module on one of said first and second transmission lines by a delay time that is a function of the sensed transmission line length between that module and said clock signal source, thereby to produce a separate local clock signal at each module.
Claim 6
Dependent Claim
20 words
The method in accordance with claim 3 wherein said delay time is inversely related to the sensed transmission line length.
Claim 7
Dependent Claim
73 words
The method in accordance with claim 3 wherein the step of sensing a length of said first and second transmission lines between said clock signal source and each module comprises the step of comparing a phase of said global clock signal as it arrives at said each module via said first transmission line to a phase of said global clock signal as it arrives at said each module via said second transmission line.
Claim 8
Dependent Claim
175 words
The method in accordance with claim 3 wherein the steps of sensing a length of said first and second transmission lines and delaying said global clock signal comprises the substeps of: comparing a phase of said global clock signal as it arrives at each module via said first transmission line to a phase of said global clock signal as it arrives at the module via said second transmission line to produce a first signal of magnitude representing said length; generating a second signal in response to said first signal wherein a magnitude of said second signal is a predetermined function of the magnitude of said first signal; and passing said global clock signal through a delay circuit to produce said local clock signal after said global clock signal arrives at said module via one of said first and second transmission lines, the delay circuit delaying said global clock signal by said delay time, said delay time being controlled in accordance with a magnitude of said second signal provided as control input to said delay circuit.
Claim 9
Dependent Claim
69 words
The method in accordance with claim 6 wherein the step of generating said second signal comprises the substeps of: storing data values at separate addresses of an addressable memory; addressing said addressable memory in accordance with the magnitude of said first signal such that said addressable memory reads out one of said stored data values; and producing said second signal magnitude in accordance with the read out data value.
Claim 10
Independent Claim
156 words
A method for producing a separate local clock signal at each of a plurality of modules of a synchronous logic system in response to a global clock signal generated by a clock signal source, the method comprising the steps of: conveying the global clock signal from said clock signal source to each module via each of first and second transmission lines; delaying said global clock signal as it arrives at each module via said first transmission line by an adjustable first delay time, thereby to produce a first local clock signal at the module; delaying said global clock signal as it arrives at each module via said second transmission line by an adjustable second delay time, thereby to produce a second local clock signal at the module; and adjusting said first and second delay times in each module to provide a predetermined phase relation between the first and second local clock signals produced at each module.
Claim 11
Independent Claim
156 words
A method for producing a separate local clock signal at each of a plurality of modules of a synchronous logic system in response to a global clock signal generated by a clock signal source, the method comprising the steps of: conveying the global clock signal from said clock signal source to each module via each of first and second transmission lines; delaying said global clock signal as it arrives at each module via said first transmission line by an adjustable first delay time, thereby to produce a first local clock signal at the module; delaying said global clock signal as it arrives at each module via said second transmission line by an adjustable second delay time, thereby to produce a second local clock signal at the module; and adjusting said first and second delay times in each module to provide a predetermined phase relation between the first and second local clock signals produced at each module.
Claim 12
Dependent Claim
66 words
The method in accordance with claim 8 wherein the first and second transmission lines are of substantially equal length between the clock signal source and each module but wherein a velocity of global clock signal propagation of said first transmission line is M times that of a velocity of global clock signal propagation of said second transmission line, where M is a number other than one.
Claim 13
Dependent Claim
28 words
The method in accordance with claim 9 wherein a ratio of said second delay time to said first delay time is substantially equal to M for each module.
Claim 14
Independent Claim
124 words
An apparatus for producing a separate local clock signal at each of a plurality of modules of a synchronous logic system in response to a global clock signal generated by a clock signal source, the apparatus comprising: a transmission line for conveying the global clock signal from said clock signal source to each module; and deskewing means for continuously sensing a length of said transmission line between said clock signal source and each module and for concurrently delaying said global clock signal as it arrives at each module via said transmission line by a delay time that is a function of the sensed transmission line length between the module and said clock signal source, thereby to produce the local clock signal at the module.
Claim 15
Independent Claim
124 words
An apparatus for producing a separate local clock signal at each of a plurality of modules of a synchronous logic system in response to a global clock signal generated by a clock signal source, the apparatus comprising: a transmission line for conveying the global clock signal from said clock signal source to each module; and deskewing means for continuously sensing a length of said transmission line between said clock signal source and each module and for concurrently delaying said global clock signal as it arrives at each module via said transmission line by a delay time that is a function of the sensed transmission line length between the module and said clock signal source, thereby to produce the local clock signal at the module.
Claim 16
Dependent Claim
31 words
The apparatus in accordance with claim 11 wherein said delay time in each module is inversely related to the sensed transmission line length between the clock signal source and the module.
Claim 17
Independent Claim
180 words
An apparatus for producing separate local clock signals to a plurality of modules of a synchronous logic system in response to a global clock signal generated by a clock signal source, wherein the local clock signals are substantially in phase with one another, the apparatus comprising: a first transmission line for conveying the global clock signal from said clock signal source to each module; a second transmission line for conveying the global clock signal from said clock signal source to each module, the first and second transmission lines, the first and second transmission lines being of substantially equal length between the clock signal source and each module but having substantially dissimilar velocities of global clock signal propagation; and deskewing means associated with each module for sensing a length of said first and second transmission lines between said clock signal source and its associated module and delaying said global clock signal as it arrives at its associated module on one of said first and second transmission lines by a delay time that is a function of the sensed transmission line length.
Claim 18
Independent Claim
180 words
An apparatus for producing separate local clock signals to a plurality of modules of a synchronous logic system in response to a global clock signal generated by a clock signal source, wherein the local clock signals are substantially in phase with one another, the apparatus comprising: a first transmission line for conveying the global clock signal from said clock signal source to each module; a second transmission line for conveying the global clock signal from said clock signal source to each module, the first and second transmission lines, the first and second transmission lines being of substantially equal length between the clock signal source and each module but having substantially dissimilar velocities of global clock signal propagation; and deskewing means associated with each module for sensing a length of said first and second transmission lines between said clock signal source and its associated module and delaying said global clock signal as it arrives at its associated module on one of said first and second transmission lines by a delay time that is a function of the sensed transmission line length.
Claim 19
Dependent Claim
20 words
The apparatus in accordance with claim 13 wherein said delay time is inversely related to the sensed transmission line length.
Claim 20
Dependent Claim
54 words
The apparatus in accordance with claim 13 wherein said deskewing means comprises means for comparing a phase of said global clock signal as it arrives at the associated module via said first transmission line to a phase of said global clock signal as it arrives at the associated module via said second transmission line.
Claim 21
Dependent Claim
152 words
The apparatus in accordance with claim 13 wherein said deskewing means comprises: means for comparing a phase of said global clock signal as it arrives at the associated module via said first transmission line to a phase of said global clock signal as it arrives at the associated module via said second transmission line to produce a first signal of magnitude representing said length; means for generating a second signal in response to said first signal wherein a magnitude of said second signal is a predetermined function of the magnitude of said first signal; and delay means for delaying said global clock signal by said delay time after said global clock signal arrives at said module via one of said first and second transmission lines to produce said local clock signal, said delay time being controlled in accordance with the magnitude of said second signal supplied as input to said delay means.
Claim 22
Dependent Claim
72 words
The apparatus in accordance with claim 16 wherein said means for generating said second signal comprises: an addressable memory for storing data values at separate addresses; means for addressing said addressable memory in accordance with the magnitude of said first signal such that said addressable memory reads out an addressed one of said stored data values; and means for producing said second signal magnitude in accordance with the read out data value.
Claim 23
Independent Claim
193 words
An apparatus for producing a separate local clock signal at each of a plurality of modules of a synchronous logic system in response to a global clock signal generated by a clock signal source, wherein the local clock signals are substantially in phase with one another, the apparatus comprising: a first transmission line for conveying the global clock signal from said clock signal source to each module; first delay means associated with each module for delaying said global clock signal as it arrives at each module via said first transmission line by an adjustable first delay time, thereby to produce a first local clock signal for the associated module; second delay means associated with each module for delaying said global clock signal as it arrives at each module via said second transmission line by an adjustable second delay time, thereby to produce a second local clock signal at the module; and means associated with each module for adjusting said first and second delay times of the first and second delay means associated with the module to provide a predetermined phase relation between the first and second local clock signals of the associated module.
Claim 24
Independent Claim
193 words
An apparatus for producing a separate local clock signal at each of a plurality of modules of a synchronous logic system in response to a global clock signal generated by a clock signal source, wherein the local clock signals are substantially in phase with one another, the apparatus comprising: a first transmission line for conveying the global clock signal from said clock signal source to each module; first delay means associated with each module for delaying said global clock signal as it arrives at each module via said first transmission line by an adjustable first delay time, thereby to produce a first local clock signal for the associated module; second delay means associated with each module for delaying said global clock signal as it arrives at each module via said second transmission line by an adjustable second delay time, thereby to produce a second local clock signal at the module; and means associated with each module for adjusting said first and second delay times of the first and second delay means associated with the module to provide a predetermined phase relation between the first and second local clock signals of the associated module.
Claim 25
Dependent Claim
46 words
The apparatus in accordance with claim 18 wherein a velocity of global clock signal propagation of said first transmission line is M times that of a velocity of global clock signal propagation of said second transmission line, where M is a number varying substantially from one.
Claim 26
Dependent Claim
35 words
The apparatus in accordance with claim 19 wherein a ratio of the second delay time of said second delay means to the first delay time of said first delay means is substantially equal to M.
Claim 27
Dependent Claim
191 words
For a synchronous logic system comprising a host unit and a plurality of logic modules distant from the host unit, wherein the host unit includes a clock signal source generating a global clock signal, a method for producing a separate local clock signal at each module and for conveying data signals between said host unit and each module, the method comprising the steps of: conveying the global clock signal from said clock signal source to each module via a transmission line; sensing a length of said transmission line between said clock signal source and each module; delaying said global clock signal as it arrives at each module via said transmission line by a delay time that is a function of the sensed transmission line length between said clock signal source and said module, thereby to produce the local clock signal at that module; conveying data signals between the host unit and each of said modules via a data line; and delaying said data signals at each of said modules by said delay time that is a function of the sensed transmission line length between said clock signal source and said module.
Claim 28
Dependent Claim
191 words
For a synchronous logic system comprising a host unit and a plurality of logic modules distant from the host unit, wherein the host unit includes a clock signal source generating a global clock signal, a method for producing a separate local clock signal at each module and for conveying data signals between said host unit and each module, the method comprising the steps of: conveying the global clock signal from said clock signal source to each module via a transmission line; sensing a length of said transmission line between said clock signal source and each module; delaying said global clock signal as it arrives at each module via said transmission line by a delay time that is a function of the sensed transmission line length between said clock signal source and said module, thereby to produce the local clock signal at that module; conveying data signals between the host unit and each of said modules via a data line; and delaying said data signals at each of said modules by said delay time that is a function of the sensed transmission line length between said clock signal source and said module.
Claim 29
Independent Claim
211 words
An apparatus for producing separate local clock signals at a plurality of modules of a synchronous logic system in response to a global clock signal generated by a clock signal source within a host unit of the synchronous logic system, and for conveying data signals between the host unit and each of said modules, the apparatus comprising: a first transmission line for conveying the global clock signal from said clock signal source to each module; a second transmission line for conveying the global clock signal from said clock signal source to each module, the first and second transmission lines; a data line for conveying said data signals between said host unit and each of said modules; and deskewing means associated with each module for sensing a phase difference between the global clock signal arriving at the at the associated module on said first and second transmission lines, delaying the global clock arriving at one of said first and second transmission lines at the associated module by a delay time that is a function of the sensed phase difference, thereby to produce a local clock signal at the associated module, and for conveying said data signals between said data line and the associated module with a delay equal to said delay time.
Claim 30
Independent Claim
211 words
An apparatus for producing separate local clock signals at a plurality of modules of a synchronous logic system in response to a global clock signal generated by a clock signal source within a host unit of the synchronous logic system, and for conveying data signals between the host unit and each of said modules, the apparatus comprising: a first transmission line for conveying the global clock signal from said clock signal source to each module; a second transmission line for conveying the global clock signal from said clock signal source to each module, the first and second transmission lines; a data line for conveying said data signals between said host unit and each of said modules; and deskewing means associated with each module for sensing a phase difference between the global clock signal arriving at the at the associated module on said first and second transmission lines, delaying the global clock arriving at one of said first and second transmission lines at the associated module by a delay time that is a function of the sensed phase difference, thereby to produce a local clock signal at the associated module, and for conveying said data signals between said data line and the associated module with a delay equal to said delay time.
Claim 31
Dependent Claim
92 words
The apparatus in accordance with claim 22 wherein the first and second transmission lines and said data line are of substantially equal length between the clock signal source and each module but wherein a velocity of global clock signal propagation of said first transmission line is M times that of a velocity of global clock signal propagation of said second transmission line, where M is a number other than one, and wherein a velocity of data signal propagation of said data line is substantially equal to that of said first transmission line.
Claim 32
Independent Claim
312 words
An apparatus for producing a separate local clock signal at each of a plurality of modules of a synchronous logic system in response to a global clock signal generated by a clock signal source, for conveying data signals between the host unit and each of said modules, the apparatus comprising: a first transmission line for conveying the global clock signal from said clock signal source to each module; a second transmission line for conveying the global clock signal from said clock signal source to each module; first delay means associated with each module for delaying said global clock signal as it arrives at each module via said first transmission line by an adjustable first delay time, thereby to produce a first local clock signal for the associated module; second delay means associated with each module for delaying said global clock signal as it arrives at each module via said second transmission line by an adjustable second delay time, thereby to produce a second local clock signal at the module; third delay means associated with each module for delaying said data signals between said data line and the associated module by said an adjustable first delay time; and means associated with each module for adjusting said first and second delay times to provide a predetermined phase relation between the first and second local clock signals of the associated module, wherein a velocity of global clock signal propagation of said first transmission line is M times that of a velocity of global clock signal propagation of said second transmission line, where M is a number varying substantially from one, wherein a velocity of signal propagation of the data line is substantially equal to the velocity of propagation of the first transmission line and wherein a ratio of the second delay time to the first delay time in each module is substantially equal to M.
Claim 33
Independent Claim
312 words
An apparatus for producing a separate local clock signal at each of a plurality of modules of a synchronous logic system in response to a global clock signal generated by a clock signal source, for conveying data signals between the host unit and each of said modules, the apparatus comprising: a first transmission line for conveying the global clock signal from said clock signal source to each module; a second transmission line for conveying the global clock signal from said clock signal source to each module; first delay means associated with each module for delaying said global clock signal as it arrives at each module via said first transmission line by an adjustable first delay time, thereby to produce a first local clock signal for the associated module; second delay means associated with each module for delaying said global clock signal as it arrives at each module via said second transmission line by an adjustable second delay time, thereby to produce a second local clock signal at the module; third delay means associated with each module for delaying said data signals between said data line and the associated module by said an adjustable first delay time; and means associated with each module for adjusting said first and second delay times to provide a predetermined phase relation between the first and second local clock signals of the associated module, wherein a velocity of global clock signal propagation of said first transmission line is M times that of a velocity of global clock signal propagation of said second transmission line, where M is a number varying substantially from one, wherein a velocity of signal propagation of the data line is substantially equal to the velocity of propagation of the first transmission line and wherein a ratio of the second delay time to the first delay time in each module is substantially equal to M.
Claim 34
Independent Claim
140 words
An apparatus for generating an output signal indicating a magnitude of signal skew in a first transmission line comprising: a pulse generator for generating an electrical pulse; a phase detector, the first transmission line conveying said pulse from said pulse generator to said phase detector; and a second transmission line for separately conveying said pulse from said pulse generator circuit to said phase detector, wherein the first and second transmission lines have similar length between said pulse generator and said phase detector but have dissimilar velocities of signal propagation, wherein the phase detector produces an output signal indicating a phase difference between arrival times of said pulse on said first and second transmission lines, and wherein said phase difference is proportional to a magnitude of signal skew in said first transmission line between said pulse generator and said phase detector.
Claim 35
Independent Claim
140 words
An apparatus for generating an output signal indicating a magnitude of signal skew in a first transmission line comprising: a pulse generator for generating an electrical pulse; a phase detector, the first transmission line conveying said pulse from said pulse generator to said phase detector; and a second transmission line for separately conveying said pulse from said pulse generator circuit to said phase detector, wherein the first and second transmission lines have similar length between said pulse generator and said phase detector but have dissimilar velocities of signal propagation, wherein the phase detector produces an output signal indicating a phase difference between arrival times of said pulse on said first and second transmission lines, and wherein said phase difference is proportional to a magnitude of signal skew in said first transmission line between said pulse generator and said phase detector.
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| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 2000-12-08 | 2001-06-09 | 2001-12-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-12-08 | 2005-06-09 | 2005-12-09 | $3760.00 | Window Closed / Lapsed |
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