Patent US5696939A successfully refreshed from Google Patents.
US5696939A
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Apparatus and method using a semaphore buffer for semaphore instructions
Assignee: Institute for Development of Emerging Architectures LLC
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Filing: 1995-09-29
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Granted: 1997-12-09
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Expires: 2015-09-29
Abstract
Abstract A simplified semaphore method and apparatus for simultaneous execution of multiple semaphore instructions and for enforcement of necessary ordering. A central processing unit having an instruction pipeline is coupled with a data cache arrangement including a semaphore buffer, a data cache, and the semaphore execution unit. An initial semaphore instruction having one or more operands and a semaphore address are transmitted from the instruction pipeline to the semaphore buffer, which in turn are transmitted from the semaphore buffer to the semaphore execution unit. The semaphore address of the initial semaphore instruction is transmitted from the instruction pipeline to the data cache to retrieve initial semaphore data stored within the data cache at a location in a data line of the data cache as identified by the semaphore address. The semaphore instruction is executed within the semaphore execution unit by operating upon the initial semaphore data and the one or more semaphore operands so as to produce processed semaphore data, which is then stored within the data cache. Since the semaphore buffer provides for entries of multiple semaphore instructions, the semaphore buffer initiates simultaneous execution of multiple semaphore instructions, as needed.
Inventors
- 👤 Sorin Iacobovici
- 👤 Dean A. Mulla
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 22:05
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/38; G06F9/3824; G06F9/3834; G06F9/30003; G06F9/3004; G06F9/30076; G06F9/30087; G06F9/3885; G06F9/46; G06F9/52
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
196 words
A method comprising the steps of: providing a central processing unit having an instruction pipeline; providing a data cache arrangement including a semaphore buffer, a data cache, and a semaphore execution unit; transmitting an initial semaphore instruction having one or more semaphore operands and a semaphore address from the instruction pipeline to the semaphore buffer; transmitting the semaphore address of the initial semaphore instruction to the data cache; retrieving initial semaphore data stored within the data cache at a location in a data line as identified by the semaphore address of the initial semaphore instruction; transmitting the initial semaphore data from the data cache to the semaphore execution unit; transmitting the initial semaphore instruction and the one or more semaphore operands from the semaphore buffer to the semaphore execution unit; executing the initial semaphore instruction within the semaphore execution unit by operating upon the initial semaphore data and the one or more semaphore operands so as to produce processed semaphore data; and completing execution of the initial semaphore instruction by storing the processed semaphore data within the data cache at the location in the data line identified by the semaphore address of the initial semaphore instruction.
Claim 2
Independent Claim
196 words
A method comprising the steps of: providing a central processing unit having an instruction pipeline; providing a data cache arrangement including a semaphore buffer, a data cache, and a semaphore execution unit; transmitting an initial semaphore instruction having one or more semaphore operands and a semaphore address from the instruction pipeline to the semaphore buffer; transmitting the semaphore address of the initial semaphore instruction to the data cache; retrieving initial semaphore data stored within the data cache at a location in a data line as identified by the semaphore address of the initial semaphore instruction; transmitting the initial semaphore data from the data cache to the semaphore execution unit; transmitting the initial semaphore instruction and the one or more semaphore operands from the semaphore buffer to the semaphore execution unit; executing the initial semaphore instruction within the semaphore execution unit by operating upon the initial semaphore data and the one or more semaphore operands so as to produce processed semaphore data; and completing execution of the initial semaphore instruction by storing the processed semaphore data within the data cache at the location in the data line identified by the semaphore address of the initial semaphore instruction.
Claim 3
Dependent Claim
106 words
A method as in claim 1 further comprising: transmitting a subsequent semaphore instruction having a semaphore address from the instruction pipeline to the semaphore buffer; and using the semaphore buffer to generate an interlock signal if the processed semaphore data of the initial semaphore instruction is not yet stored in the data cache and if the data line identified by the semaphore address of the initial semaphore instruction is the same as a data line identified by the semaphore address of the subsequent semaphore instruction; interlocking the instruction pipeline in response to the interlock signal until the processed semaphore data is stored in the data cache.
Claim 4
Dependent Claim
145 words
A method as in claim 1 further comprising: transmitting a subsequent load instruction having an address from the instruction pipeline to the semaphore buffer; and using the semaphore buffer to generate an interlock signal, if the processed semaphore data of the initial semaphore instruction is not yet stored in the data cache, if the data line identified by the semaphore address of the initial semaphore instruction is the same as a data line identified by the address of the subsequent load instruction, and if there is any byte overlap between the location in the data line identified by the semaphore address of the initial semaphore instruction and a location in the data line as identified by the address of the subsequent load instruction; and interlocking the instruction pipeline in response to the interlock signal until the processed semaphore data is stored in the data cache.
Claim 5
Dependent Claim
145 words
A method as in claim 1 further comprising: transmitting a subsequent store instruction having an address from the instruction pipeline to the semaphore buffer; and using the semaphore buffer to generate an interlock signal, if the processed semaphore data of the initial semaphore instruction is not yet stored in the data cache, if the data line identified by the semaphore address of the initial semaphore instruction is the same as a data line identified by the address of the subsequent load instruction, and if there is any byte overlap between the location in the data line identified by the semaphore address of the initial semaphore instruction and a location in the data line as identified by the address of the subsequent load instruction; and interlocking the instruction pipeline in response to the interlock signal until the processed semaphore data is stored in the data cache.
Claim 6
Dependent Claim
51 words
A method as in claim 1 wherein: the semaphore instruction is a fetch and add instruction; the one or more operands includes a first operand; and the step of executing the semaphore instruction includes adding the first operand to the initial semaphore data so as to produce the processed semaphore data.
Claim 7
Dependent Claim
92 words
A method as in claim 1 wherein: the semaphore instruction is a compare and exchange instruction; the one or more operands includes a first operand and a second operand; the step of executing the semaphore instruction includes comparing the first operand to the initial semaphore data so as to determine whether the first operand value is equal to the initial semaphore data; and the step of storing the processed semaphore data includes storing the second operand as the processed semaphore data if the first operand is equal to the initial semaphore data.
Claim 8
Independent Claim
111 words
A method comprising the steps of: providing a data cache arrangement including a semaphore buffer, a data cache, and a semaphore execution unit; storing in the semaphore buffer an initial semaphore instruction having a semaphore address; retrieving initial semaphore data stored within the data cache; executing the initial semaphore instruction within the execution unit by operating upon the initial semaphore data so as to produce processed semaphore data; and initiating simultaneous execution of semaphore instructions by using the semaphore buffer to store a subsequent semaphore instruction and to begin execution of the subsequent semaphore instruction before the processed semaphore data of the initial semaphore instruction is stored in the data cache.
Claim 9
Independent Claim
111 words
A method comprising the steps of: providing a data cache arrangement including a semaphore buffer, a data cache, and a semaphore execution unit; storing in the semaphore buffer an initial semaphore instruction having a semaphore address; retrieving initial semaphore data stored within the data cache; executing the initial semaphore instruction within the execution unit by operating upon the initial semaphore data so as to produce processed semaphore data; and initiating simultaneous execution of semaphore instructions by using the semaphore buffer to store a subsequent semaphore instruction and to begin execution of the subsequent semaphore instruction before the processed semaphore data of the initial semaphore instruction is stored in the data cache.
Claim 10
Dependent Claim
28 words
A method as in claim 7 further comprising the step of completing execution of the initial semaphore instruction by storing the processed semaphore data within the data cache.
Claim 11
Independent Claim
162 words
An apparatus comprising: a central processing unit including an instruction pipeline for providing a semaphore instruction having one or more semaphore operands and a semaphore address; and a data cache arrangement including: a semaphore buffer coupled with the instruction pipeline for receiving the semaphore instruction and the semaphore operand; a data cache coupled with the instruction pipeline for receiving the semaphore address and for providing initial semaphore data stored within the data cache in a data line as identified by the semaphore address; a semaphore execution unit coupled with the semaphore buffer for receiving the semaphore instruction and the semaphore operand, and coupled with the data cache for receiving the initial semaphore data, the semaphore execution unit being adapted for executing the semaphore instruction by operating upon the initial semaphore data and the one or more operands so as to produce processed semaphore data and adapted for storing the processed semaphore data back in the data line identified by the semaphore address.
Claim 12
Independent Claim
162 words
An apparatus comprising: a central processing unit including an instruction pipeline for providing a semaphore instruction having one or more semaphore operands and a semaphore address; and a data cache arrangement including: a semaphore buffer coupled with the instruction pipeline for receiving the semaphore instruction and the semaphore operand; a data cache coupled with the instruction pipeline for receiving the semaphore address and for providing initial semaphore data stored within the data cache in a data line as identified by the semaphore address; a semaphore execution unit coupled with the semaphore buffer for receiving the semaphore instruction and the semaphore operand, and coupled with the data cache for receiving the initial semaphore data, the semaphore execution unit being adapted for executing the semaphore instruction by operating upon the initial semaphore data and the one or more operands so as to produce processed semaphore data and adapted for storing the processed semaphore data back in the data line identified by the semaphore address.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-12-08 | 2001-06-09 | 2001-12-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-12-08 | 2005-06-09 | 2005-12-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-12-08 | 2009-06-09 | 2009-12-09 | $7700.00 | Window Closed / Lapsed |