Patent US5696017A successfully refreshed from Google Patents.
US5696017A
Expired / Lapsed
US
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Method of fabricating a semiconductor device with a capacitor structure having increased capacitance
Assignee: NEC Electronics Corp
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Filing: 1994-12-27
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Granted: 1997-12-09
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Expires: 2014-12-27
Abstract
Abstract A semiconductor integrated circuit device with a capacitor structure having a large capacitance per unit surface is disclosed, wherein a contact hole is formed in an insulator layer, a metal electrode with or without a rugged surface is formed in the contact hole by an ion beam vapor deposition of metal, and a capacitor insulator layer is formed on a surface of the metal electrode. The metal electrode is integral with a contact metal. The capacitor structure comprises the metal electrode integral with the contact metal and the capacitor insulator layer which are buried in the contact hole. The device is improved in planarization, reduction of parasitic resistance, maintenance of capacitance and mass production ability.
Inventors
- 👤 Kazuyoshi Ueno
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 11:23
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/01; H10B12/02; H10B12/03; H10B12/033; H10D; H10D1/00; H10D1/01; H10D1/041; H10D1/042; H10D1/60; H10D1/68; H10D1/692; H10D1/711; H10D1/712
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
111 words
A method for fabricating a semiconductor integrated circuit device including a switching transistor having a conducting region, comprising the steps of: forming a contact hole in an insulator layer; depositing an electrode metal having a thickness smaller than the diameter of the contact hole on a surface of the insulator layer so that the electrode metal is directly electrically connected to the conducting region of the switching transistor; polishing and removing the electrode metal existing in portions other than an inner periphery of the contact hole; and forming a capacitor insulator layer on a surface of the electrode metal, said capacitor insulator layer and said electrode metal comprising a common metal.
Claim 2
Independent Claim
111 words
A method for fabricating a semiconductor integrated circuit device including a switching transistor having a conducting region, comprising the steps of: forming a contact hole in an insulator layer; depositing an electrode metal having a thickness smaller than the diameter of the contact hole on a surface of the insulator layer so that the electrode metal is directly electrically connected to the conducting region of the switching transistor; polishing and removing the electrode metal existing in portions other than an inner periphery of the contact hole; and forming a capacitor insulator layer on a surface of the electrode metal, said capacitor insulator layer and said electrode metal comprising a common metal.
Claim 3
Dependent Claim
32 words
The method for fabricating a semiconductor integrated circuit device according to claim 1, wherein the electrode metal is formed from TiN and the capacitor insulator layer is formed from TiO 2 .
Claim 4
Dependent Claim
25 words
The method for fabricating a semiconductor integrated circuit device according to claim 1, wherein the electrode metal and the capacitor insulator layer are formed integrally.
Claim 5
Dependent Claim
55 words
The method for fabricating a semiconductor integrated circuit device according to claim 1, further comprising the step of depositing a contact metal on the surface of the insulator layer prior to depositing the electrode metal so that the electrode metal is electrically connected to the conducting region of the switching transistor through the contact metal.
Claim 6
Dependent Claim
21 words
The method for fabricating a semiconductor integrated circuit device according to claim 4, wherein the contact metal is formed from Ti.
Claim 7
Dependent Claim
27 words
The method for fabricating a semiconductor integrated circuit device according to claim 1, further comprising the step of depositing an upper electrode metal over the capacitor layer.
Claim 8
Dependent Claim
22 words
The method for fabricating a semiconductor integrated circuit device according to claim 6, wherein the upper electrode metal is formed from TiN.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-12-08 | 2001-06-09 | 2001-12-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-12-08 | 2005-06-09 | 2005-12-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-12-08 | 2009-06-09 | 2009-12-09 | $7700.00 | Window Closed / Lapsed |