US5694392A
Expired / Lapsed
US
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Timing system for mobile cellular radio receivers
Assignee: Philips Semiconductors Inc
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Filing: 1995-10-30
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Granted: 1997-12-02
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Expires: 2015-10-30
Abstract
Abstract A hardware timing system for a cellular telephone comprises a master counter and a slave counter. The slave counter controls timing window generators in synchronism with the time frame of the local base station. The phases of timing frames of other base stations are monitored using the master counter.
Inventors
- 👤 Philippe Gaglione
- 👤 John Whittle
- 👤 Bruno Bocaert
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 08:57
CPC Classifications
H; H04; H04B; H04B7/00; H04B7/24; H04B7/26; H04B7/2662; H04B7/2671; H04B7/2678; H04B7/2684; H04W; H04W56/00; H04W56/0035
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
199 words
A timing system for a mobile receiver of a cellular communication network wherein base stations communicate with mobile receivers by means of a time division multiple access protocol defined in a repetitive time frame, the phase of the time frame being different for different ones of the base stations, said system comprising: means for providing a system clock signal; a master cyclic counter for counting said system clock and defining a counting cycle corresponding to said time frame; a slave counter for counting said system clock; a first comparator for comparing a first set count value with a count from said slave counter to provide a starting signal; a second comparator for comparing a second set count value with a count value from said slave counter to provide a terminating signal; means for determining a first master count value of said master counter in response to an event having a predetermined position within said time frame; means for providing a second master count value in accordance with said first master count value and said predetermined position; and a third comparator for comparing a count of said master counter with said second master count value to reset said slave counter.
Claim 2
Dependent Claim
199 words
A timing system for a mobile receiver of a cellular communication network wherein base stations communicate with mobile receivers by means of a time division multiple access protocol defined in a repetitive time frame, the phase of the time frame being different for different ones of the base stations, said system comprising: means for providing a system clock signal; a master cyclic counter for counting said system clock and defining a counting cycle corresponding to said time frame; a slave counter for counting said system clock; a first comparator for comparing a first set count value with a count from said slave counter to provide a starting signal; a second comparator for comparing a second set count value with a count value from said slave counter to provide a terminating signal; means for determining a first master count value of said master counter in response to an event having a predetermined position within said time frame; means for providing a second master count value in accordance with said first master count value and said predetermined position; and a third comparator for comparing a count of said master counter with said second master count value to reset said slave counter.
Claim 3
Dependent Claim
24 words
A timing system according to claim 1 wherein said means for determining said first master count value comprises a latch responsive to said event.
Claim 4
Dependent Claim
21 words
A timing system according to claim 1 wherein said means for providing said second master count value includes a storage register.
Claim 5
Dependent Claim
23 words
A timing system according to claim 1 and further comprising a timing window generator responsive to said starting signal and said terminating signal.
Claim 6
Dependent Claim
33 words
A timing system according to claim 1 and further comprising a fourth comparator for comparing a count in said master counter with a selectable count to generate an interrupt signal for a microprocessor.
Claim 7
Dependent Claim
151 words
A timing system for use in a time division multiple access communication system, said timing system comprising: means for providing a system clock signal; a master cyclic counter for counting said system clock and defining a counting cycle; a slave counter for counting said system clock; a plurality of timing window generating means each timing window generating means including means for comparing a first respective set count value with a count from said slave counter to provide a starting signal and means for comparing a second respective set count value with a count value from said slave counter to provide a terminating signal; means for determining a first master count value of said master counter in response to a control signal; means for providing a second master count value; and a comparator for comparing a count of said master counter with said second master count value to reset said slave counter.
Claim 8
Dependent Claim
151 words
A timing system for use in a time division multiple access communication system, said timing system comprising: means for providing a system clock signal; a master cyclic counter for counting said system clock and defining a counting cycle; a slave counter for counting said system clock; a plurality of timing window generating means each timing window generating means including means for comparing a first respective set count value with a count from said slave counter to provide a starting signal and means for comparing a second respective set count value with a count value from said slave counter to provide a terminating signal; means for determining a first master count value of said master counter in response to a control signal; means for providing a second master count value; and a comparator for comparing a count of said master counter with said second master count value to reset said slave counter.
Claim 9
Dependent Claim
24 words
A timing system according to claim 6 wherein said means for determining said first master count value comprises a latch responsive to control signal.
Claim 10
Dependent Claim
21 words
A timing system according to claim 6 wherein said means for providing said second master count value includes a storage register.
Claim 11
Dependent Claim
33 words
A timing system according to claim 6 and further comprising a second comparator for comparing a count in said master counter with a selectable count to generate an interrupt signal for a microprocessor.
Claim 12
Dependent Claim
161 words
A timing system comprising: means for providing a system clock signal; a master cyclic counter for counting said system clock and defining a counting cycle; a slave counter for counting said system clock; at least one timing window generating means each timing window generating means including means for comparing a first respective set count value with a count from said slave counter to provide a starting signal and means for comparing a second respective set count value with a count value from said slave counter to provide a terminating signal; means for determining a first master count value of said master counter in response to a control signal; means for providing a second master count value; a comparator for comparing a count of said master counter with said second master count value to reset said slave counter; and a second comparator for comparing a count in said master counter with a selectable count to generate an interrupt signal for a microprocessor.
Claim 13
Dependent Claim
161 words
A timing system comprising: means for providing a system clock signal; a master cyclic counter for counting said system clock and defining a counting cycle; a slave counter for counting said system clock; at least one timing window generating means each timing window generating means including means for comparing a first respective set count value with a count from said slave counter to provide a starting signal and means for comparing a second respective set count value with a count value from said slave counter to provide a terminating signal; means for determining a first master count value of said master counter in response to a control signal; means for providing a second master count value; a comparator for comparing a count of said master counter with said second master count value to reset said slave counter; and a second comparator for comparing a count in said master counter with a selectable count to generate an interrupt signal for a microprocessor.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-12-01 | 2001-06-02 | 2001-12-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-12-01 | 2005-06-02 | 2005-12-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-12-01 | 2009-06-02 | 2009-12-02 | $7700.00 | Window Closed / Lapsed |