Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
271 words
Timing logic in a portable telephone of the GSM system employing time division multiple access (TDMA) and its channel structure consisting of consecutive numbered TDMA frames with 8 time intervals each, the base station sending the transmission advancing value to each portable telephone individually, and on a broadcast control channel frequency correction burst, synchronizing burst and the system parameters, characterized in that the logic comprises - a frame length counter (2), which on overflow increments the frame number counter (1) and in which the value from a frame length register (3) containing the standard frame length or the value from a the correction register (4) is loaded, - a neighbouring base stations' timing register (9), in which are stored the frame number difference of the own base station and at least six neighbouring base stations, and the timing difference of the frame bars, and from which the timing difference value of one frame timing bar at a time is loaded into a base stations timing difference counter (6) and from there further into a neighbouring base stations' timing difference counter (6), which, on overflow, indicates the moment from which the reception of the synchronizing frame or BCCH data from a neighbouring base station is commenced, - own base station's timing registers (10), in which are stored the transmission advancing value given by the own base station and the value of the absolute reception time interval, and from which the advancing value is loaded into a transmission advancement timing register (8), wherefrom it is loaded into a transmission advancing timing counter (7), which when on overflow, gives the start pulse for transmission.
Claim 2
Dependent Claim
21 words
Timing logic according to claim 1, characterized in that the frame length correction register (4) is employed for changing the timing.
Claim 3
Dependent Claim
33 words
Timing logic according to claim 2, characterized in that if the reception time interval (Rx) changes from larger to smaller, the frame number counter (1) is incremented during the frame length correction frame.
Claim 4
Dependent Claim
125 words
Timing logic according to claim 1, characterized in that the timing difference and frame number difference relative to the own base station of at least six strongest neighbouring base stations is calculated in that the rough value of the timing difference obtained in frequency correction burst is loaded from the base station timing difference register (5) into the neighbouring base stations' timing difference counter (6), which receiving data of each neighbouring base station generates a frame interrupt at the moment of receiving the synchronizing frame of the neighbouring base station, and from the synchronizing frame said timing difference and the frame number difference are calculated, these being stored in the base stations timing difference register (5) and in the neighbouring base stations timing register (9).
Claim 5
Dependent Claim
73 words
Timing logic according to claim 4, characterized in that when at base station switching, a frame length correction frame is calculated on the basis of the timing difference stored in the neighbouring base stations timing register (9) which correction frame is being loaded into the frame length correction register (4), and a new frame number is calculated from the base station frame number difference to be set in the frame number counter (1).
Claim 6
Dependent Claim
58 words
Timing logic according to claim 1, characterized in that the advancing value transmitted by the base station is stored in the own base station's timing register (10), wherefrom it is loaded into the transmission advancement timing register (7), the contents of which are then loaded into the transmission advancement timing counter (7), which generates a transmission start pulse.
Claim 7
Dependent Claim
43 words
Timing logic according to claim 1, characterized in that the relative frame timing bar is used in the timing, whereby the timing logic maintains the reception time interval (Rx) always at zero time interval regardless of what its absolute time interval may be.