Integrated circuit including fully testable small scale read only memory constructed of level sensitive scan device shift register latches

Claim 1

A microprocessor chip comprising: (1) a digital video decoder including a. a first Huffman decoder for receiving variable length encoded digital video data and expanding the data; b. an inverse quantizer for receiving data from the first Huffman decoder and dequantizing the data; c. an inverse discrete cosine transformer for receiving dequantizied data from the inverse quantizer and inverse discrete cosine transforming the data; d. a second Huffman decoder for receiving variable length encoded digital video data and expanding the data; e. a motion compensator for receiving data from (i) the second Huffman decoder, and (ii) a past frame storage and a future frame storage, and forming motion compensated image data therefrom; f. a summer for summing image data from the motion compensator and the inverse discrete cosine transformer; and g. said past frame storage and said future frame storage, both receiving inverse discrete cosine transformed data from the summer; and (2) an on-chip shift register latch Read Only Memory as a look-up memory for the inverse discrete cosine transformer, said shift register latch Read Only Memory comprising: a. a first shift register latch for receiving input data from a pull-up resistor; b. a second shift register latch adapted for use as a read only memory cell for storing the input data from the first shift register latch; c. a selector and ROM address decoder for selecting shift register latch memory cells to be read from the shift register latch Read Only Memory to the inverse discrete cosine transformer; and d. a Read Only Memory data output from the shift register latch Read Only Memory to the inverse discrete cosine transformer.