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US5693546A
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Methods of forming thin film transistors having lightly-doped drain and source regions therein
Assignee: Samsung Display Co Ltd
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Filing: 1996-06-06
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Granted: 1997-12-02
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Expires: 2016-06-06
Abstract
Abstract Methods of forming field effect transistors include the steps of forming a composite of layers including an amorphous silicon layer (a--Si), a silicon dioxide layer thereon and a silicon nitride layer on the silicon dioxide layer. A polycrystalline silicon conductive layer is then formed on the silicon nitride layer by depositing and patterning polycrystalline silicon. The polycrystalline silicon conductive layer is then oxidized using thermal oxidation techniques to form an oxide outerlayer. During this step, a portion of the polycrystalline silicon conductive layer will be consumed to define a gate electrode. Dopants of first conductivity type are then implanted into a top surface of the silicon nitride layer, using the oxide outerlayer and the gate electrode as a mask, to form relatively lightly doped preliminary source and drain regions in the amorphous silicon layer. The oxide outerlayer is then removed preferably using a buffered oxide etchant (BOE) solution which does not etch silicon nitride. Following this, dopants of first conductivity type are again implanted into the amorphous silicon layer, using the gate electrode as a mask. The second implantation step causes the formation of a field effect transistor having self-aligned source and drain regions, self-aligned lightly doped source and drain region extensions (LDS, LDD) and a channel region therebetween which has the same length as the gate electrode. By forming the channel region to have the same length as the gate electrode, improved device characteristics can be achieved.
Inventors
- 👤 Byeong-Yun Nam
- 👤 Sang-won Lee
- 👤 Jin-hong Kim
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 20:08
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/031; H10D30/0312; H10D30/0314; H10P; H10P10/00; H10D30/0321; H10D30/60; H10D30/67; H10D30/6704; H10D30/6713; H10D30/6715
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
171 words
A method of forming a thin-film field effect transistor, comprising the steps of: forming an oxide layer on an amorphous silicon region; forming a silicon nitride layer on the oxide layer, opposite the amorphous silicon region; forming a conductive layer on the silicon nitride layer, opposite the oxide layer; oxidizing the conductive layer to form a gate electrode having opposing edges and an oxide outerlayer on the opposing edges; forming preliminary source and drain regions in the amorphous silicon region by implanting dopants through the oxide layer and the silicon nitride layer and into the amorphous silicon region using the gate electrode and oxide outerlayer as an implant mask; removing the oxide outerlayer from the opposing edges of the gate electrode; and forming source and drain regions in the preliminary source and drain regions, respectively, and forming lightly doped source and drain region extensions between the source and drain regions by implanting dopants through the oxide layer and into the amorphous silicon region using the gate electrode as an implant mask.
Claim 2
Independent Claim
171 words
A method of forming a thin-film field effect transistor, comprising the steps of: forming an oxide layer on an amorphous silicon region; forming a silicon nitride layer on the oxide layer, opposite the amorphous silicon region; forming a conductive layer on the silicon nitride layer, opposite the oxide layer; oxidizing the conductive layer to form a gate electrode having opposing edges and an oxide outerlayer on the opposing edges; forming preliminary source and drain regions in the amorphous silicon region by implanting dopants through the oxide layer and the silicon nitride layer and into the amorphous silicon region using the gate electrode and oxide outerlayer as an implant mask; removing the oxide outerlayer from the opposing edges of the gate electrode; and forming source and drain regions in the preliminary source and drain regions, respectively, and forming lightly doped source and drain region extensions between the source and drain regions by implanting dopants through the oxide layer and into the amorphous silicon region using the gate electrode as an implant mask.
Claim 3
Dependent Claim
23 words
The method of claim 1, wherein said conductive layer forming step comprises forming a polycrystalline silicon conductive layer on the silicon nitride layer.
Claim 4
Dependent Claim
31 words
The method of claim 2, wherein said source and drain regions forming step is followed by the step of etching the silicon nitride layer using the gate electrode as a mask.
Claim 5
Dependent Claim
31 words
The method of claim 2, wherein said source and drain regions forming step is preceded by the step of etching the silicon nitride layer using the gate electrode as a mask.
Claim 6
Dependent Claim
21 words
The method of claim 4, wherein said oxide outerlayer removing step comprises removing the oxide outerlayer using a buffered oxide etchant.
Claim 7
Dependent Claim
28 words
The method of claim 3, wherein said silicon nitride layer etching step comprises etching the silicon nitride layer with a plasma containing CF 4 and CHF 3 .
Claim 8
Independent Claim
167 words
A method of forming a field effect transistor having lightly doped source and drain region extensions, comprising the steps of: forming an oxide layer on a semiconductor substrate; forming a nitride layer on the oxide layer, opposite the semiconductor substrate; forming a conductive layer on the nitride layer, opposite the oxide layer; oxidizing the conductive layer to form a gate electrode having opposing edges and an oxide outerlayer on the opposing edges; forming preliminary source and drain regions in the substrate by implanting dopants through the oxide layer and the nitride layer and into the substrate using the gate electrode and oxide outerlayer as an implant mask; removing the oxide outerlayer from the opposing edges of the gate electrode; and forming source and drain regions in the preliminary source and drain regions, respectively, and forming lightly doped source and drain region extensions between the source and drain regions by implanting dopants through the oxide layer and into the substrate using the gate electrode as an implant mask.
Claim 9
Independent Claim
167 words
A method of forming a field effect transistor having lightly doped source and drain region extensions, comprising the steps of: forming an oxide layer on a semiconductor substrate; forming a nitride layer on the oxide layer, opposite the semiconductor substrate; forming a conductive layer on the nitride layer, opposite the oxide layer; oxidizing the conductive layer to form a gate electrode having opposing edges and an oxide outerlayer on the opposing edges; forming preliminary source and drain regions in the substrate by implanting dopants through the oxide layer and the nitride layer and into the substrate using the gate electrode and oxide outerlayer as an implant mask; removing the oxide outerlayer from the opposing edges of the gate electrode; and forming source and drain regions in the preliminary source and drain regions, respectively, and forming lightly doped source and drain region extensions between the source and drain regions by implanting dopants through the oxide layer and into the substrate using the gate electrode as an implant mask.
Claim 10
Dependent Claim
38 words
The method of claim 7, further comprising the step of etching the nitride layer using the gate electrode as a mask prior to said step of forming source and drain regions in the preliminary source and drain regions.
Claim 11
Dependent Claim
28 words
The method of claim 1, wherein said step of oxidizing the conductive layer to form a gate electrode is preceded by the step of patterning the conductive layer.
Claim 12
Dependent Claim
28 words
The method of claim 7, wherein said step of oxidizing the conductive layer to form a gate electrode is preceded by the step of patterning the conductive layer.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 2000-12-01 | 2001-06-02 | 2001-12-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-12-01 | 2005-06-02 | 2005-12-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-12-01 | 2009-06-02 | 2009-12-02 | $7700.00 | Window Closed / Lapsed |