Semiconductor memory device having voltage booster circuit coupled to a bit line charging/equalizing circuit or switch

Claim 2

A semiconductor memory device comprising: first and second bit line pairs, each of said bit line pairs having first and second bit lines; a boosted voltage generating circuit, connected to a power supply voltage, for constantly generating a boosted voltage having a voltage level higher than a voltage level of said power supply voltage; a sense amplifier, connected to said first and second bit line pairs, for sensing and amplifying potential differences between the first and second bit lines of said first and second bit line pairs; a first charging/equalizing circuit, connected to the first and second bit lines of said first bit line pair, responsive to a first charging/equalizing control signal for charging the first and second bit lines of said first bit line pair with a first charging voltage, and for equalizing the first and second bit lines of said first bit line pair at the same first equalized voltage level; a first level converting circuit, connected to said first charging/equalizing circuit and to said boosted voltage generating circuit, for converting a first input control signal into a first converted control signal at the voltage level of the boosted voltage, and for outputting the first converted control signal as the first charging/equalizing control signal; a second charging/equalizing circuit, connected to the first and second bit lines of said second bit line pair, responsive to a second charging/equalizing control signal for charging the first and second bit lines of said second bit line pair with a second charging voltage, and for equalizing the first and second bit lines of said second bit line pair at the same second equalized voltage level; a second level converting circuit, connected to said second charging/equalizing circuit and to said boosted voltage generating circuit, for converting a second input control signal into a second converted control signal at the voltage level of the boosted voltage, and for outputting the second converted control signal as the second charging/equalizing control signal; a first switch, connected to said first bit line pair and to said sense amplifier, responsive to a first switch control signal having a switch control signal voltage level equal to the voltage level of the boosted voltage for selectively connecting said first bit line pair to said sense amplifier; and a second switch, connected to said second bit line pair and to said sense amplifier, responsive to a second switch control signal having a switch control signal voltage level equal to the voltage level of the boosted voltage for selectively connecting said second bit line pair to said sense amplifier.

Claim 3

The semiconductor memory device according to claim 1, wherein: said first charging/equalizing control signal is equalized to the voltage level of the boosted voltage when the first and second bit lines of said first bit line pair are being charged with the first charging voltage; said second charging/equalizing control signal is equalized to the voltage level of the boosted voltage when the first and second bit lines of said second bit line pair are being charged with the second charging voltage; and the first and second switch control signals are equalized to the voltage level of the boosted voltage during a period of time other than when the first and second bit lines of said first and second bit line pairs are being charged with the first and second charging voltages, respectively.

Claim 4

The semiconductor memory device according to claim 1, wherein said first charging/equalizing circuit includes: a first MOS transistor having a source-drain path connected between the first bit line of said first bit line pair and a first node which is supplied with the first charging voltage, and a gate which is supplied with the first charging/equalizing control signal; a second MOS transistor having a source-drain path connected between the second bit line of said first bit line pair and said first node, and a gate which is supplied with the first charging/equalizing control signal; and a third MOS transistor having a source-drain path connected between the first and second bit lines of said first bit line pair, and a gate which is supplied with the first charging/equalizing control signal; and wherein said second charging/equalizing circuit includes: a fourth MOS transistor having a source-drain path connected between the first bit line of said second bit line pair and a second node which is supplied with the second charging voltage, and a gate which is supplied with the second charging/equalizing control signal; a fifth MOS transistor having a source-drain path connected between the second bit line of said second bit line pair and said second node, and a gate which is supplied with the second charging/equalizing control signal; and a sixth MOS transistor having a source-drain path connected between the first and second bit lines of said second bit line pair, and a gate which is supplied with the second charging/equalizing control signal.

Claim 5

The semiconductor memory device according to claim 3, wherein said first, second, third, fourth, fifth and sixth MOS transistors have the same channel conductivity type.

Claim 6

The semiconductor memory device according to claim 1, wherein said boosted voltage generating circuit includes: a reference voltage generating circuit for generating a reference voltage; a boosting circuit responsive to a boosting circuit control signal for generating the boosted voltage by boosting the power supply voltage; a voltage converting circuit for converting the boosted voltage to a converted voltage having a voltage level lower than the voltage level of the boosted voltage; and a voltage comparing circuit for comparing the reference voltage and the converted voltage to generate a comparison signal, and for outputting the comparison signal as said boosting circuit control signal.

Claim 7

The semiconductor memory device according to claim 1, wherein said first charging/equalizing control signal has a second voltage level equal to a ground voltage and said second charging/equalizing control signal has a second voltage level equal to the ground voltage.

Claim 8

The semiconductor memory device according to claim 1, further comprising: a third level converting circuit, connected to said first switch and to said boosted voltage generating circuit, for converting a third input control signal into a third converted control signal at the voltage level of the boosted voltage, and for outputting the third converted control signal as the first switch control signal; and a fourth level converting circuit, connected to said second switch and to said boosted voltage generating circuit, for converting a fourth input control signal into a fourth converted control signal at the voltage level of the boosted voltage, and for outputting the fourth converted control signal as the second switch control signal.

Claim 9

A semiconductor memory device comprising: first and second bit line pairs, each of said bit line pairs having first and second bit lines; a boosted voltage generating circuit, connected to a power supply voltage, for constantly generating a boosted voltage having a voltage level higher than a voltage level of said power supply voltage; a sense amplifier, connected to said first and second bit line pairs, for sensing and amplifying potential differences between the first and second bit lines of said first and second bit line pairs; a first charging/equalizing circuit, connected to the first and second bit lines of said first bit line pair, responsive to a first charging/equalizing control signal, for charging the first and second bit lines of said first bit line pair with a first charging voltage, and for equalizing the first and second bit lines of said first bit line pair at the same first equalized voltage level; a second charging/equalizing circuit, connected to the first and second bit lines of said second bit line pair, responsive to a second charging/equalizing control signal, for charging the first and second bit lines of said second bit line pair with a second charging voltage, and for equalizing the first and second bit lines of said second bit line pair at the same second equalized voltage level; a first switch, connected to said first bit line pair and to said sense amplifier, responsive to a first switch control signal for selectively connecting said first bit line pair to said sense amplifier; a first level converting circuit, connected to said first switch and to said boosted voltage generating circuit, for converting a first input control signal into a first converted control signal at the voltage level of the boosted voltage, and for outputting the first converted control signal as the first switch control signal; a second switch, connected to said second bit line pair and to said sense amplifier, responsive to a second switch control signal for selectively connecting said second bit line pair to said sense amplifier; and a second level converting circuit, connected to said second switch and to said boosted voltage generating circuit, for converting a second input control signal into a second converted control signal at the voltage level of the boosted voltage, and for outputting the second converted control signal as the second switch control signal.

Claim 10

A semiconductor memory device comprising: first and second bit line pairs, each of said bit line pairs having first and second bit lines; a boosted voltage generating circuit, connected to a power supply voltage, for constantly generating a boosted voltage having a voltage level higher than a voltage level of said power supply voltage; a sense amplifier, connected to said first and second bit line pairs, for sensing and amplifying potential differences between the first and second bit lines of said first and second bit line pairs; a first charging/equalizing circuit, connected to the first and second bit lines of said first bit line pair, responsive to a first charging/equalizing control signal, for charging the first and second bit lines of said first bit line pair with a first charging voltage, and for equalizing the first and second bit lines of said first bit line pair at the same first equalized voltage level; a second charging/equalizing circuit, connected to the first and second bit lines of said second bit line pair, responsive to a second charging/equalizing control signal, for charging the first and second bit lines of said second bit line pair with a second charging voltage, and for equalizing the first and second bit lines of said second bit line pair at the same second equalized voltage level; a first switch, connected to said first bit line pair and to said sense amplifier, responsive to a first switch control signal for selectively connecting said first bit line pair to said sense amplifier; a first level converting circuit, connected to said first switch and to said boosted voltage generating circuit, for converting a first input control signal into a first converted control signal at the voltage level of the boosted voltage, and for outputting the first converted control signal as the first switch control signal; a second switch, connected to said second bit line pair and to said sense amplifier, responsive to a second switch control signal for selectively connecting said second bit line pair to said sense amplifier; and a second level converting circuit, connected to said second switch and to said boosted voltage generating circuit, for converting a second input control signal into a second converted control signal at the voltage level of the boosted voltage, and for outputting the second converted control signal as the second switch control signal.

Claim 11

A semiconductor memory device comprising: a first memory cell array including a plurality of memory cells which are connected to first word lines and to first and second bit lines; a first sense amplifier adjacent to said first memory cell array; a second memory cell array adjacent to said first sense amplifier and including a plurality of memory cells which are connected to second word lines and to third and fourth bit lines; a second sense amplifier adjacent to said second memory cell array; a third memory cell array adjacent to said second sense amplifier and including a plurality of memory cells which are connected to third word lines and to fifth and sixth bit lines; a first charging/equalizing circuit, located between said first memory cell array and said first sense amplifier and responsive to a first charging/equalizing signal, for charging the first and second bit lines in said first memory cell array with a first charging voltage and for equalizing the first and second bit lines at the same first equalized voltage level; a first switch, located between said first charging/equalizing circuit and said first sense amplifier and responsive to a first switch control signal, for connecting said first and second bit lines in said first memory cell array to said first sense amplifier; a second charging/equalizing circuit located between said second memory cell array and said first sense amplifier and responsive to a second charging/equalizing signal, for charging the third and fourth bit lines in said second memory cell array with a second charging voltage and for equalizing the third and fourth bit lines at the same second equalized voltage level; a second switch, located between said second charging/equalizing circuit and said first sense amplifier and responsive to a second switch control signal, for connecting the third and fourth bit lines in said second memory cell array to said first sense amplifier; a third charging/equalizing circuit located between said second memory cell array and said second sense amplifier and responsive to the second charging/equalizing signal, for charging the third and fourth bit lines in said second memory cell array with a third charging voltage and for equalizing the third and fourth bit lines at the same third equalized voltage level; a third switch, located between said third charging/equalizing circuit and said second sense amplifier and responsive to a third switch control signal, for connecting the third and fourth bit lines in said second memory cell array to said second sense amplifier; a fourth charging/equalizing circuit, located between said third memory cell array and said second sense amplifier and responsive to a third charging/equalizing signal for charging the fifth and sixth bit lines in said third memory cell array with a fourth charging voltage and for equalizing the fifth and sixth bit lines at the same fourth equalized voltage level; and a fourth switch, located between said fourth charging/equalizing circuit and said second sense amplifier and responsive to the first switch control signal, for connecting the fifth and sixth bit lines in said third memory cell array to said second sense amplifier, wherein, when data in the memory cells in said second memory cell array is read out, the word lines in said second memory cell array are selectively set at a high level and the first switch control signal is set at a low level, to bring said first and fourth switches into a non-conductive state, and at the same time the second charging/equalizing signal is set at a low level to bring said second and third charging/equalizing circuits into a disabled condition.

Claim 12

A semiconductor memory device comprising: a first memory cell array including a plurality of memory cells which are connected to first word lines and to first and second bit lines; a first sense amplifier adjacent to said first memory cell array; a second memory cell array adjacent to said first sense amplifier and including a plurality of memory cells which are connected to second word lines and to third and fourth bit lines; a second sense amplifier adjacent to said second memory cell array; a third memory cell array adjacent to said second sense amplifier and including a plurality of memory cells which are connected to third word lines and to fifth and sixth bit lines; a first charging/equalizing circuit, located between said first memory cell array and said first sense amplifier and responsive to a first charging/equalizing signal, for charging the first and second bit lines in said first memory cell array with a first charging voltage and for equalizing the first and second bit lines at the same first equalized voltage level; a first switch, located between said first charging/equalizing circuit and said first sense amplifier and responsive to a first switch control signal, for connecting said first and second bit lines in said first memory cell array to said first sense amplifier; a second charging/equalizing circuit located between said second memory cell array and said first sense amplifier and responsive to a second charging/equalizing signal, for charging the third and fourth bit lines in said second memory cell array with a second charging voltage and for equalizing the third and fourth bit lines at the same second equalized voltage level; a second switch, located between said second charging/equalizing circuit and said first sense amplifier and responsive to a second switch control signal, for connecting the third and fourth bit lines in said second memory cell array to said first sense amplifier; a third charging/equalizing circuit located between said second memory cell array and said second sense amplifier and responsive to the second charging/equalizing signal, for charging the third and fourth bit lines in said second memory cell array with a third charging voltage and for equalizing the third and fourth bit lines at the same third equalized voltage level; a third switch, located between said third charging/equalizing circuit and said second sense amplifier and responsive to a third switch control signal, for connecting the third and fourth bit lines in said second memory cell array to said second sense amplifier; a fourth charging/equalizing circuit, located between said third memory cell array and said second sense amplifier and responsive to a third charging/equalizing signal for charging the fifth and sixth bit lines in said third memory cell array with a fourth charging voltage and for equalizing the fifth and sixth bit lines at the same fourth equalized voltage level; and a fourth switch, located between said fourth charging/equalizing circuit and said second sense amplifier and responsive to the first switch control signal, for connecting the fifth and sixth bit lines in said third memory cell array to said second sense amplifier, wherein, when data in the memory cells in said second memory cell array is read out, the word lines in said second memory cell array are selectively set at a high level and the first switch control signal is set at a low level, to bring said first and fourth switches into a non-conductive state, and at the same time the second charging/equalizing signal is set at a low level to bring said second and third charging/equalizing circuits into a disabled condition.

Claim 13

The semiconductor memory device according to claim 9, wherein, when data in the memory cells in said second memory cell array is read out, the second switch control signal is at a low level for rendering the second switch non-conductive and the third switch control signal is at a high level for rendering said third switch conductive.

Claim 14

The semiconductor memory device according to claim 9, further comprising: a boosted voltage generating circuit, connected to a power supply voltage, for constantly generating a boosted voltage having a voltage level higher than a voltage level of said power supply voltage.

Claim 15

The semiconductor memory device according to claim 11, wherein the first, second, and third charging/equalizing signals each has a first level corresponding to the level of the boosted voltage.

Claim 16

The semiconductor memory device according to claim 11, further comprising: a first level converting circuit, connected to said first charging/equalizing circuit and to said boosted voltage generating circuit, for converting a first input control signal into a first converted control signal at the voltage level of the boosted voltage, and for outputting the first converted control signal as the first charging/equalizing signal; a second level converting circuit, connected to said second and third charging/equalizing circuits and to said boosted voltage generating circuit, for converting a second input control signal into a second converted control signal at the voltage level of the boosted voltage, and for outputting the second converted control signal as the second charging/equalizing signal; and a third level converting circuit, connected to said fourth charging/equalizing circuit and to said boosted voltage generating circuit, for converting a third input control signal into a third converted control signal at the voltage level of the boosted voltage, and for outputting the third converted control signal as the third charging/equalizing signal.

Claim 17

A semiconductor memory device comprising: first and second bit line pairs, each of said bit line pairs having first and second bit lines; a boosted voltage generating circuit, connected to a power supply voltage, for constantly generating a boosted voltage having a voltage level higher than a voltage level of said power supply voltage; a sense amplifier, connected to said first and second bit line pairs, for sensing and amplifying potential differences between the first and second bit lines of said first and second bit line pairs; a first charging/equalizing circuit, connected to the first and second bit lines of said first bit line pair, responsive to a first charging/equalizing control signal, for charging the first and second bit lines of said first bit line pair with a first charging voltage, and for equalizing the first and second bit lines of said first bit line pair at the same first equalized voltage level; a first level converting circuit, connected to said first charging/equalizing circuit and to said boosted voltage generating circuit, for converting a first input control signal into a first converted control signal at the voltage level of the boosted voltage, and for outputting the first converted control signal as the first charging/equalizing control signal; a second charging/equalizing circuit, connected to the first and second bit lines of said second bit line pair, responsive to a second charging/equalizing control signal, for charging the first and second bit lines of said second bit line pair with a second charging voltage, and for equalizing the first and second bit lines of said second bit line pair at the same second equalized voltage level; a second level converting circuit, connected to said second charging/equalizing circuit and to said boosted voltage generating circuit, for converting a second input control signal into a second converted control signal at the voltage level of the boosted voltage, and for outputting the second converted control signal as the second charging/equalizing control signal; a first switch, connected to said first bit line pair and to said sense amplifier, responsive to a first switch control signal for selectively connecting said first bit line pair to said sense amplifier; and a second switch, connected to said second bit line pair and to said sense amplifier, responsive to a second switch control signal for selectively connecting said second bit line pair to said sense amplifier.

Claim 18

A semiconductor memory device comprising: first and second bit line pairs, each of said bit line pairs having first and second bit lines; a boosted voltage generating circuit, connected to a power supply voltage, for constantly generating a boosted voltage having a voltage level higher than a voltage level of said power supply voltage; a sense amplifier, connected to said first and second bit line pairs, for sensing and amplifying potential differences between the first and second bit lines of said first and second bit line pairs; a first charging/equalizing circuit, connected to the first and second bit lines of said first bit line pair, responsive to a first charging/equalizing control signal, for charging the first and second bit lines of said first bit line pair with a first charging voltage, and for equalizing the first and second bit lines of said first bit line pair at the same first equalized voltage level; a first level converting circuit, connected to said first charging/equalizing circuit and to said boosted voltage generating circuit, for converting a first input control signal into a first converted control signal at the voltage level of the boosted voltage, and for outputting the first converted control signal as the first charging/equalizing control signal; a second charging/equalizing circuit, connected to the first and second bit lines of said second bit line pair, responsive to a second charging/equalizing control signal, for charging the first and second bit lines of said second bit line pair with a second charging voltage, and for equalizing the first and second bit lines of said second bit line pair at the same second equalized voltage level; a second level converting circuit, connected to said second charging/equalizing circuit and to said boosted voltage generating circuit, for converting a second input control signal into a second converted control signal at the voltage level of the boosted voltage, and for outputting the second converted control signal as the second charging/equalizing control signal; a first switch, connected to said first bit line pair and to said sense amplifier, responsive to a first switch control signal for selectively connecting said first bit line pair to said sense amplifier; and a second switch, connected to said second bit line pair and to said sense amplifier, responsive to a second switch control signal for selectively connecting said second bit line pair to said sense amplifier.

Claim 19

A semiconductor memory device comprising: first and second bit line pairs, each of said bit line pairs having first and second bit lines; a boosted voltage generating circuit, connected to a power supply voltage, for constantly generating a boosted voltage having a voltage level higher than a voltage level of said power supply voltage; a sense amplifier, connected to said first and second bit line pairs, for sensing and amplifying potential differences between the first and second bit lines of said first and second bit line pairs; a first charging/equalizing circuit, connected to the first and second bit lines of said first bit line pair, responsive to a first charging/equalizing control signal, for charging the first and second bit lines of said first bit line pair with a first charging voltage, and for equalizing the first and second bit lines of said first bit line pair at the same first equalized voltage level; a first level converting circuit, connected to said first charging/equalizing circuit and to said boosted voltage generating circuit, for converting a first input control signal into a first converted control signal at the voltage level of the boosted voltage, and for outputting the first converted control signal as the first charging/equalizing control signal; a second charging/equalizing circuit, connected to the first and second bit lines of said second bit line pair, responsive to a second charging/equalizing control signal, for charging the first and second bit lines of said second bit line pair with a second charging voltage, and for equalizing the first and second bit lines of said second bit line pair at the same second equalized voltage level; and a second level converting circuit, connected to said second charging/equalizing circuit and to said boosted voltage generating circuit, for convening a second input control signal into a second converted control signal at the voltage level of the boosted voltage, and for outputting the second converted control signal as the second charging/equalizing control signal.

Claim 20

A semiconductor memory device comprising: first and second bit line pairs, each of said bit line pairs having first and second bit lines; a boosted voltage generating circuit, connected to a power supply voltage, for constantly generating a boosted voltage having a voltage level higher than a voltage level of said power supply voltage; a sense amplifier, connected to said first and second bit line pairs, for sensing and amplifying potential differences between the first and second bit lines of said first and second bit line pairs; a first charging/equalizing circuit, connected to the first and second bit lines of said first bit line pair, responsive to a first charging/equalizing control signal, for charging the first and second bit lines of said first bit line pair with a first charging voltage, and for equalizing the first and second bit lines of said first bit line pair at the same first equalized voltage level; a first level converting circuit, connected to said first charging/equalizing circuit and to said boosted voltage generating circuit, for converting a first input control signal into a first converted control signal at the voltage level of the boosted voltage, and for outputting the first converted control signal as the first charging/equalizing control signal; a second charging/equalizing circuit, connected to the first and second bit lines of said second bit line pair, responsive to a second charging/equalizing control signal, for charging the first and second bit lines of said second bit line pair with a second charging voltage, and for equalizing the first and second bit lines of said second bit line pair at the same second equalized voltage level; and a second level converting circuit, connected to said second charging/equalizing circuit and to said boosted voltage generating circuit, for convening a second input control signal into a second converted control signal at the voltage level of the boosted voltage, and for outputting the second converted control signal as the second charging/equalizing control signal.

Claim 21

A semiconductor memory device comprising: first and second bit line pairs, each of said bit line pairs having first and second bit lines; a boosted voltage generating circuit, connected to a power supply voltage, for constantly generating a boosted voltage having a voltage level higher than a voltage level of said power supply voltage; a sense amplifier, connected to said first and second bit line pairs, for sensing and amplifying potential differences between the first and second bit lines of said first and second bit line pairs; a first switch, connected to said first bit line pair and to said sense amplifier, responsive to a first switch control signal for selectively connecting said first bit line pair to said sense amplifier; a first level converting circuit, connected to said first switch and to said boosted voltage generating circuit, for converting a first input control signal into a first converted control signal at the voltage level of the boosted voltage, and for outputting the first converted control signal as the first switch control signal; a second switch, connected to said second bit line pair and to said sense amplifier, responsive to a second switch control signal for selectively connecting said second bit line pair to said sense amplifier; and a second level converting circuit, connected to said second switch and to said boosted voltage generating circuit, for converting a second input control signal into a second converted control signal at the voltage level of the boosted voltage, and for outputting the second converted control signal as the second switch control signal.

Claim 22

A semiconductor memory device comprising: first and second bit line pairs, each of said bit line pairs having first and second bit lines; a boosted voltage generating circuit, connected to a power supply voltage, for constantly generating a boosted voltage having a voltage level higher than a voltage level of said power supply voltage; a sense amplifier, connected to said first and second bit line pairs, for sensing and amplifying potential differences between the first and second bit lines of said first and second bit line pairs; a first switch, connected to said first bit line pair and to said sense amplifier, responsive to a first switch control signal for selectively connecting said first bit line pair to said sense amplifier; a first level converting circuit, connected to said first switch and to said boosted voltage generating circuit, for converting a first input control signal into a first converted control signal at the voltage level of the boosted voltage, and for outputting the first converted control signal as the first switch control signal; a second switch, connected to said second bit line pair and to said sense amplifier, responsive to a second switch control signal for selectively connecting said second bit line pair to said sense amplifier; and a second level converting circuit, connected to said second switch and to said boosted voltage generating circuit, for converting a second input control signal into a second converted control signal at the voltage level of the boosted voltage, and for outputting the second converted control signal as the second switch control signal.