Logic circuit having voltage booster

Claim 2

A logic circuit having a signal input end (A, I) and a signal output end (B, G, J), for boosting a voltage of an input signal by voltage boosting means (15, 30, 40, 17) when a voltage level of the input signal supplied to said signal input end (A, I) is changed to a predetermined level, so as to supply a boosted voltage to said signal output end (B, G, J), characterized in that said logic circuit comprising: boosted voltage retaining means (70) having an output end (M) so as to steadily produce a boosted voltage boosted higher than a power source voltage (VC); and switching means (80, 90, 100, 110) arranged between an output end of said boosted voltage retaining means and said signal output end (B, G, J).

Claim 3

A circuit according to claim 1, characterized in that said switching means comprising a depletion type MOS transistor (81) connected between said signal output end (B, G, J) and said boosted voltage retaining means (70) and means for keeping the depletion type MOS transistor (81) in cut-off state before the level of said input signal is changed to a predetermined level.

Claim 4

A circuit according to claim 1, characterized in that said switching means comprises an enhancement type MOS transistor (101) connected between said signal output end (B, G, J) and said boosted voltage retaining means (70) and booster means connected to the gate of said enhancement type MOS transistor (101).

Claim 5

A circuit according to claim 1, characterized in that said switching means (80, 90) comprises first, second and third depletion-type MOS transistors (81, 91, 82, 92, 83, 93) and a first end (N), said first depletion-type MOS transistor (.81, 91) being inserted between said output end (M) of said boosted voltage retaining means (70) and said first end (N), said second depletion-type MOS transistor (82, 92) being inserted between the power source voltage (VC) and said first end (N), said third depletion-type MOS transistor (83, 93) being inserted between said first end (N) and said signal output end (B), a gate of said second depletion-type MOS transistor (82, 92) receiving a signal which causes said second depletion-type MOS transistor (82, 92) to turn on before the voltage of the input signal is boosted by said voltage boosting means (15, 30), and gates of said first and third -depletion-type MOS transistors (81, 91, 83, 93) receiving a signal which causes said first and third depletion-type MOS transistors (81, 91, 83, 93) to simultaneously turn on before the voltage of the input signal is boosted by said voltage boosting means (15, 30) .

Claim 6

A circuit according to claim 1, characterized in that said switching means (100) comprises first and second enhancement-type MOS transistors (101, 102), an oscillator (103), a capacitor (104) and a first end (S), said first enhancement-type MOS transistor (101) being inserted between said output end (M) of said boosted voltage retaining means (70) and said signal output end (J), said second enhancement-type MOS transistor (102) being inserted between said signal input end (I) and said first end (S) connected to a gate of said first enhancement-type MOS transistor (101), and said capacitor (104) being inserted between an output end (T) of said oscillator (103) and said first end (S).

Claim 7

A circuit according to claim 1, characterized in that said switching means (110) comprises first, second, third and fourth enhancement-type MOS transistors (101, 105, 106, 107), an oscillator (103), a capacitor (104) and first, second and third ends (U, S, B'), said first enhancement-type MOS transistor (101) being inserted between an output end (M) of said boosted voltage retaining means (70) and said signal output end (B), said capacitor having one end which is connected to an output end (T) of said oscillator (103) and the other end which is connected to said first end (U), said second enhancement-type MOS transistor (105) being inserted between said first end (U) and said second end (S) connected to a gate of said first enhancement-type MOS transistor (101), said third enhancement-type MOS transistor (106) being inserted between said first end (U) and said third end (B') at which a voltage corresponding to the input signal is obtained, and said fourth enhancement-type MOS transistor (107) being inserted between said second end (S) and said third end (B').

Claim 8

A circuit according to claim 4, characterized in that said first depletion-type MOS transistor (81, 91) has a transconductance gm which is sufficiently greater than a transconductance gm of said third depletion-type MOS transistor (83, 93).

Claim 9

A logic circuit characterized by comprising: a plurality of signal input ends (A, I); a plurality of signal output ends (B, G, J); a plurality of voltage boosting means (15, 30, 40, 17) for boosting a plurality of voltages of input signals when voltage levels of the plurality of input signals respectively supplied to said plurality of signal input ends (A, I) are changed to a predetermined level, respectively, so as to supply boosted voltages to said plurality of output ends (B, G, J); boosted voltage retaining means (70) having an output end (M) to steadily produce the boosted voltage boosted higher than a power source voltage (VC); and a plurality of switching means (80, 90, 100, 110) each connected between said output end (M) and a corresponding one of said plurality of signal output ends (B, G, J).

Claim 10

A logic circuit characterized by comprising: a plurality of signal input ends (A, I); a plurality of signal output ends (B, G, J); a plurality of voltage boosting means (15, 30, 40, 17) for boosting a plurality of voltages of input signals when voltage levels of the plurality of input signals respectively supplied to said plurality of signal input ends (A, I) are changed to a predetermined level, respectively, so as to supply boosted voltages to said plurality of output ends (B, G, J); boosted voltage retaining means (70) having an output end (M) to steadily produce the boosted voltage boosted higher than a power source voltage (VC); and a plurality of switching means (80, 90, 100, 110) each connected between said output end (M) and a corresponding one of said plurality of signal output ends (B, G, J).

Claim 11

A circuit according to claim 8, characterized in that said switching means (80, 90) comprises first, second and third depletion-type MOS transistors (81, 91, 82, 92, 83, 93) and a first end (N), said first depletion-type MOS transistor (81, 91) being inserted between said output end (M) of said boosted voltage retaining means (70) and said first end (N), said second depletion-type MOS transistor (82, 92) being inserted between the power source voltage (VC) and said first end (N), said third depletion-type MOS transistor (83, 93) being inserted between said first end (N) and said signal output end (B), a gate of said second depletion-type MOS transistor (82, 92) receiving a signal which causes said second depletion-type MOS transistor (82, 92) to turn on before the voltage of the input signal is boosted by said voltage boosting means (15, 30), and gates of said first and third depletion-type MOS transistors (81, 91, 83, 93) receiving a signal which causes said first and third depletion-type MOS transistors (81, 91, 83, 93) to simultaneously turn on before the voltage of the input signal is boosted by said voltage boosting means (15, 30) .

Claim 12

A circuit according to claim 8, characterized in that said switching means (100) comprises first and second enhancement-type MOS transistors (101, 102), an oscillator (103), a capacitor (104) and a first end (S), said first enhancement-type MOS transistor (101) being inserted between said output end (M) of said boosted voltage retaining means (70) and said signal output end (J), said second enhancement-type MOS transistor (102) being inserted between said signal input end (I) and said first end (S) connected to a gate of said first enhancement-type MOS transistor (101), and said capacitor (104) being inserted between an output end (T) of said oscillator (103) and said first end (S).

Claim 13

A circuit according to claim 8, characterized in that said switching means (110) comprises first, second, third and fourth enhancement-type MOS transistors (101, 105, 106, 107), an oscillator (103), a capacitor (104) and first, second and third ends (U, S, B'), said first enhancement-type MOS transistor (101) being inserted between an output end (M) of said boosted voltage retaining means (70) and said signal output end (B), said capacitor having one end which is connected to an output end (T) of said oscillator (103) and the other end which is connected to said first end -(U), said second enhancement-type MOS transistor (105) being inserted between said first end (U) and said second end (S) connected to a gate of said first enhancement-type MOS transistor (101), said third enhancement-type MOS transistor (106) being inserted between said first end (U) and said third end (B') at which a voltage corresponding to the input signal is obtained, and said fourth enhancement-type MOS transistor (107) being inserted between said second end (S) and said third end (B').

Claim 14

A circuit according to claim 9, characterized in that said first depletion-type MOS transistor (81, 91) has a transconductance gm which is sufficiently greater than a transconductance gm of said third depletion-type MOS transistor (83, 93).

Claim 15

A logic circuit characterized by comprising: a signal input end (AB); a signal output end (DB); an internal boosted voltage end (BB) for obtaining an internal boosted voltage; boosted voltage retaining means (230) having at least one output end (MA, MB) to steadily produce a boosted voltage boosted higher than a power source voltage (VC); switching means (220) arranged between said output end (MA) of said boosted voltage retaining means (230) and said internal boosted voltage end (BB); voltage boosting means (210) having at least an M OS transistor (213), a gate of which is connected to said internal boosted voltage end (BB) and which is inserted between said output end (MB) of said boosted voltage retaining means (230) and said signal output end ( D B), said voltage boosting means being adapted to supply to said internal boosted voltage end (BB) the internal boosted voltage obtained by boosting a voltage of an input signal to a voltage higher than the power source voltage (VC) when a voltage level of the input signal supplied to said signal input end (AB) is changed to a predetermined level, and to supply to said signal output end (DB) the boosted voltage from said output end (MB) of said boosted voltage retaining means (230) through said MOS transistor when the internal boosted voltage is supplied to said internal boosted voltage end (BB).

Claim 16

A logic circuit characterized by comprising: a signal input end (AB); a signal output end (DB); an internal boosted voltage end (BB) for obtaining an internal boosted voltage; boosted voltage retaining means (230) having at least one output end (MA, MB) to steadily produce a boosted voltage boosted higher than a power source voltage (VC); switching means (220) arranged between said output end (MA) of said boosted voltage retaining means (230) and said internal boosted voltage end (BB); voltage boosting means (210) having at least an M OS transistor (213), a gate of which is connected to said internal boosted voltage end (BB) and which is inserted between said output end (MB) of said boosted voltage retaining means (230) and said signal output end ( D B), said voltage boosting means being adapted to supply to said internal boosted voltage end (BB) the internal boosted voltage obtained by boosting a voltage of an input signal to a voltage higher than the power source voltage (VC) when a voltage level of the input signal supplied to said signal input end (AB) is changed to a predetermined level, and to supply to said signal output end (DB) the boosted voltage from said output end (MB) of said boosted voltage retaining means (230) through said MOS transistor when the internal boosted voltage is supplied to said internal boosted voltage end (BB).

Claim 17

A circuit according to claim 13, characterized in that said boosted voltage retaining means (230) has a first output end (MA) and a second output end (MB) respectively steadily produce first and second boosted voltages and said switching means (220) comprises first, second and third depletion-type MOS transistors (221, 222, 223) and a first end (EB), said first depletion-type MOS transistor (221) being inserted between said first output end (MA) of said boosted voltage retaining means (230) and said first end (EB), said second depletion-type MOS transistor (222) being inserted between the power source voltage (VC) and said first end (EB), said third depletion-type MOS transistor (223) being inserted between said first end (EB) and said internal boosted voltage end (BB), a gate of said second depletion-type MOS transistor (222) receiving a signal which causes said second depletion-type MOS transistor (222) to turn on before the voltage of the input signal is boosted by said voltage boosting means (210), and gates of said first and third depletion-type MOS transistors (221, 223) receiving a signal which causes said first and third depletion-type MOS transistors (221, 223) to simultaneously turn on before the voltage of the input signal is boosted by said voltage boosting means (210).

Claim 18

A circuit according to claim 14, characterized in that said first depletion-type MOS transistor (221) has a transconductance gm which is sufficiently greater than a transconductance gm of said third depletion-type MOS transistor (233).

Claim 19

A circuit according to claim 13, characterized in that said boosted voltage retaining means (230) has a first output end (MA) and a second output end ( MB ) respectively steadily produce first and second boosted voltages and said voltage boosting means (210) comprises first, second and third MOS transistors (213, 214, 211, 216), an inverter (212) and a capacitor (215), said first MOS transistor (213) being inserted between said second output end (MB) of said boosted voltage retaining means (230) and said signal output end (DB), a gate of said first MOS transistor (213) being connected to said internal boosted voltage end (BB), said inverter (212) being connected to invert a signal from said signal input end (AB), said second MOS transistor (214) being inserted between said signal output end (DB) and ground, a gate of said second MOS transistor (214) being connected to an output end of said inverter (212), and said third MOS transistor (211, 216) being inserted between said signal input end (AB) and said internal boosted voltage end (BB).

Claim 20

A circuit according to claim 16, characterized in that said first and second MOS transistors (213, 214) are of an enhancement type.

Claim 21

A logic circuit characterized by comprising: a signal input end (AB); a signal output end (DB); an internal boosted voltage end (BB) for obtaining an internal boosted voltage; boosted voltage retaining means (230) having an output end (MB) to steadily produce a boosted voltage boosted higher than a power source voltage ( V C); boosted voltage generating means (250) for producing the boosted voltage boosted higher than the power source voltage (VC) at said internal boosted voltage end (BB); voltage boosting means (210) having an MOS transistor (213) inserted between said output end ( MB ) -of said boosted voltage retaining means (230) and said signal output end (DB) such that a gate of said MOS transistor is connected to said internal boosted voltage end (BB), said voltage boosting means (210) being adapted to supply to said internal boosted voltage end (BB) the internal boosted voltage obtained by boosting a voltage of an input signal to a voltage higher than the power source voltage (VC) when a voltage level of the input signal supplied to said signal input end (AB) is changed to a predetermined level, and to supply to said signal output end (DB) the boosted voltage from said output end (MB) of said boosted voltage retaining means (230) through said MOS transistor (213) when the boosted voltage of the input signal is supplied to said internal boosted voltage end (BB).

Claim 22

A logic circuit characterized by comprising: a signal input end (AB); a signal output end (DB); an internal boosted voltage end (BB) for obtaining an internal boosted voltage; boosted voltage retaining means (230) having an output end (MB) to steadily produce a boosted voltage boosted higher than a power source voltage ( V C); boosted voltage generating means (250) for producing the boosted voltage boosted higher than the power source voltage (VC) at said internal boosted voltage end (BB); voltage boosting means (210) having an MOS transistor (213) inserted between said output end ( MB ) -of said boosted voltage retaining means (230) and said signal output end (DB) such that a gate of said MOS transistor is connected to said internal boosted voltage end (BB), said voltage boosting means (210) being adapted to supply to said internal boosted voltage end (BB) the internal boosted voltage obtained by boosting a voltage of an input signal to a voltage higher than the power source voltage (VC) when a voltage level of the input signal supplied to said signal input end (AB) is changed to a predetermined level, and to supply to said signal output end (DB) the boosted voltage from said output end (MB) of said boosted voltage retaining means (230) through said MOS transistor (213) when the boosted voltage of the input signal is supplied to said internal boosted voltage end (BB).

Claim 23

A circuit according to claim 18, characterized in that said voltage boosting means (210) comprises first, second and third MOS transistors (213, 214, 211, 216), an inverter (212) and a capacitor (215), said first MOS transistor (213) being inserted between said output end (MB) of said boosted voltage retaining means (230) and said signal output end (DB), a gate of said first MOS transistor (213) being connected to said internal boosted voltage end (BB), said inverter (212) being connected to invert a signal from said signal input end (AB), said second MOS transistor (214) being inserted between said signal output end (DB) and ground, a gate of said second MOS transistor (214) being connected to an output end of said inverter (212), and said third MOS transistor (211, 216) being inserted between said signal input end (AB) and said internal boosted voltage end (BB).

Claim 24

A circuit according to claim 19, characterized in that said first and second MOS transistors (213, 214) are of an enhancement type.

Claim 25

A logic circuit characterized by comprising: a plurality of signal input ends (AB); a plurality of signal output ends (DB); a plurality of internal boosted voltage ends (BB) for obtaining internal boosted voltages; boosted voltage retaining means (230) having at least one output end (MA, MB) to steadily produce a boosted voltage boosted higher than a power source voltage (VC); a plurality of switching means (220) respectively arranged between said output end (MA) of said boosted voltage retaining means (230) and said plurality of internal boosted voltage ends'(BB); a plurality of voltage boosting means (210) each having at least one MOS transistor (213) inserted between each of said plurality of signal output ends (DB) and said output end (MB) of said boosted voltage retaining means (230), a gate of said MOS transistor (213) being connected to a corresponding one of said plurality of internal boosted voltage ends (BB), and said plurality of voltage boosting means being adapted to boost voltages of input signals so as to respectively supply boosted voltages to said plurality of internal boosted voltage ends (BB) when voltage levels of the input signals supplied to said plurality of signal input ends (AB) are changed to a predetermined level, and to supply the boosted voltage from said output end (M B ) of said boosted voltage retaining means (230) to said plurality of signal output ends (DB) through the corresponding MOS transistors (213).

Claim 26

A logic circuit characterized by comprising: a plurality of signal input ends (AB); a plurality of signal output ends (DB); a plurality of internal boosted voltage ends (BB) for obtaining internal boosted voltages; boosted voltage retaining means (230) having at least one output end (MA, MB) to steadily produce a boosted voltage boosted higher than a power source voltage (VC); a plurality of switching means (220) respectively arranged between said output end (MA) of said boosted voltage retaining means (230) and said plurality of internal boosted voltage ends'(BB); a plurality of voltage boosting means (210) each having at least one MOS transistor (213) inserted between each of said plurality of signal output ends (DB) and said output end (MB) of said boosted voltage retaining means (230), a gate of said MOS transistor (213) being connected to a corresponding one of said plurality of internal boosted voltage ends (BB), and said plurality of voltage boosting means being adapted to boost voltages of input signals so as to respectively supply boosted voltages to said plurality of internal boosted voltage ends (BB) when voltage levels of the input signals supplied to said plurality of signal input ends (AB) are changed to a predetermined level, and to supply the boosted voltage from said output end (M B ) of said boosted voltage retaining means (230) to said plurality of signal output ends (DB) through the corresponding MOS transistors (213).