EP0535325A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Voltage generator for a memory array
Assignee: International Business Machines Corp
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Filing: 1992-08-01
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Granted: —
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Expires: 2012-08-01
Abstract
Abstract A voltage generator comprising a regulator for controlling said on-chip generator which produces a boost voltage V BST supplied to one of two inputs to each of a plurality of word line drivers in a memory array, the other input to each of said word line drivers receiving a power supply voltage V DD . Said voltage regulator comprising: means for generating a reference voltage V REF ; first differential means (33) for producing a transition voltage V X from said reference voltage V REF and said power supply voltage VDD, said transition voltage being representative of a fluctuation in said power supply voltage; first transistor means (QP3) for comparing said power supply voltage V DD with said boost voltage V BST ; second transistor (QP5) means for comparing said transition voltage V X with said reference voltage V REF ; and a latching comparator (44) coupled to receive the signal outputs from said first transistor (QP3) and said second transistor (QP5), said latching comparator outputting a boost voltage control signal for said on-chip voltage generator, said control signal operating to define the following boost voltage: V BST = - V REF + V DD - V X .
Inventors
- 👤 Sang H. Dhong
- 👤 Hyun J. Shin
- 👤 Wei Hwang
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-02 21:18
CPC Classifications
G; G11; G11C; G11C8/00; G11C8/08; G11C5/00; G11C5/14; G11C5/147
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
137 words
Voltage generator for a plurality of word line drivers of a memory array, each driver being connected so as to control one of a plurality of word lines in said array, and each of said drivers having a first input and a second input, said voltage supply circuitry including: first means for supplying a first voltage (V DD ) to said first inputs of said plurality of word line drivers (18); second means for supplying a second voltage (V BST ) to said second inputs of said word line drivers (18); and means (24, 22, 20, 25) for regulating said second voltage supplying means such that the voltage difference between said first voltage and said second voltage supplied to said word line drivers is substantially constant as said first voltage changes within a predefined first voltage range.
Claim 2
Dependent Claim
90 words
The voltage generator of claim 1, comprising: a charge reservoir (20), the charge across said reservoir comprising said second voltage (V BST ) supplied to said second inputs of said word line drivers (18); and a charge generator (22) coupled to said charge reservoir (20), said charge generator operating to charge/discharge said reservoir under control of said regulating means (24), said charging/discharging being so as to maintain said constant voltage difference between said first voltage and said second voltage as said first voltage changes within said predefined first voltage range.
Claim 3
Dependent Claim
17 words
The voltage generator of claim 1 or 2 , wherein said memory array comprises a DRAM structure.
Claim 4
Dependent Claim
37 words
The voltage generator of anyone of the claims 1 to 3, wherein said first voltage supplying means supplies the memory array power supply V DD to said first inputs of said plurality of word line drivers (18).
Claim 5
Dependent Claim
47 words
The voltage generator of anyone of the claims 1 to 4, wherein said second voltage supplying means includes means for supplying a second voltage to said word line drivers which is independent of said first voltage when said first voltage is outside said predefined first voltage range.
Claim 6
Dependent Claim
37 words
The voltage generator of claim 5, wherein said second voltage supplying means includes means for supplying a substantially constant second voltage to said word line drivers when said first voltage is outside said predefined first voltage range.
Claim 7
Dependent Claim
200 words
A voltage generator comprising a regulator for controlling said on-chip generator which produces a boost voltage V BST supplied to one of two inputs to each of a plurality of word line drivers in a memory array, the other input to each of said word line drivers receiving a power supply voltage V DD said voltage regulator comprising: means for generating a reference voltage V REF ; first differential means (33) for producing a transition voltage V X from said reference voltage V REF and said power supply voltage V DD , said transition voltage being representative of a fluctuation in said power supply voltage; first transistor means (QP3) for comparing said power supply voltage V DD with said boost voltage V BST ; second transistor (QP5) means for comparing said transition voltage V X with said reference voltage V REF ; and a latching comparator (44) coupled to receive the signal outputs from said first transistor (QP3) and said second transistor (QP5), said latching comparator outputting a boost voltage control signal for said on-chip voltage generator, said control signal operating to define the following boost voltage: V BST = - V REF + V DD - V X .
Claim 8
Dependent Claim
95 words
The voltage generator of claim 7, the regulator of which further including: second differential means (40) for producing a level shifted boost voltage from said boost voltage V BST , reference voltage V REF and power supply voltage V DD ; said first transistor (QP3) means including means for comparing said power supply voltage V DD with said level shifted boost voltage; and said latching comparator (44) outputting a boost voltage control signal to said on-chip voltage generator to define the following boost voltage: V BST = -V BASE + V DD -V X .
Claim 9
Dependent Claim
30 words
The voltage generator of claim 8, wherein said first differential (32) means and said second differential means (40) each compensate for the effects of temperature variations on the respective voltages.
Claim 10
Dependent Claim
24 words
The voltage generator of claims 7 to 9, wherein said reference voltage V REF generating means (30) comprises an on-chip bandgap reference voltage generator.
Claim 11
Dependent Claim
203 words
The voltage generator of claim 10 wherein said bandgap voltage reference generator (30) comprises: a heavily doped N-type polysilicon PMOS transistor (QPNPOLY) connected in diode configuration with its gate and drain coupled to ground potential; a heavily doped P-type polysilicon PMOS transistor (QPPOLY) connected in diode configuration, the sources of said heavily doped polysilicon PMOS transistors being connected together; at least one PMOS transistor (QP13, QP14) disposed between said commonly connected sources of said heavily doped polysilicon PMOS transistors and a power supply voltage (V DD ); first current source means (QP11, QN11) coupled to the gate of said at least one PMOS transistor for controlling the voltage across said coupled heavily doped polysilicon PMOS transistors; an NMOS transistor (QN13) disposed between the coupled gate and drain of said heavily doped P-type polysilicon PMOS transistor and ground potential; and second current source means (QP12, QN12) coupled to the gate of said NMOS transistor (QN13) for controlling the voltage level at said coupled gate and drain of said heavily doped P-type polysilicon PMOS transistor (QPPOLY), wherein the reference voltage V REF to be output from said generator comprises said voltage at said coupled gate and drain of said heavily doped P-type polysilicon PMOS transistor.
Claim 12
Dependent Claim
140 words
The voltage generator (30) of claim 11, wherein said first current source means includes a first PMOS transistor (QP11) and a first NMOS transistor (QN11), the source of said first PMOS transistor being coupled to power supply voltage and the gate and drain of said first PMOS transistor being coupled together, the drain of said first NMOS transistor being connected to said coupled gate and drain of said first PMOS transistor, the gate of said firsts NMOS transistor being connected to powers supply voltage and the source of said first NMOS transistor being connected to ground, the commonly connected gate and drain of said first PMOS transistor being connected to the gate of said at least one PMOS transistor (QP13, QP14) disposed between the commonly connected sources of the heavily doped polysilicon transistors (QNPOLY, QPPOLY) and the power supply voltage.
Claim 13
Dependent Claim
114 words
The voltage generator of claim 12, wherein said second current source means includes a second PMOS transistor (QP12) and a second NMOS transistor (QN12), the source of said second PMOS transistor being coupled to power supply voltage and the gate of said second PMOS transistor being connected to the coupled gate and drain of said first PMOS transistor (QP11), the drain of said second PMOS transistor being connected to the drain and the gate of said second NMOS transistor (QN12), the source of said second NMOS transistor being connected to ground potential, the output of said second current source means being taken at the coupled drain and gate of said second NMOS transistor (QN12).
References Cited (Backward Citations)
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