US5688710A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of fabricating a twin - well CMOS device
Assignee: Industrial Technology Research Institute
•
Filing: 1996-11-27
•
Granted: 1997-11-18
•
Expires: 2016-11-27
Abstract
Abstract A method of fabricating a twin-well integrated circuit device to implant the dopants directly through the nitride layer including steps of: The pad oxide layer and nitride layer are formed on a P-type semiconductor silicon wafer. Then, the alignment mark photoresist pattern is formed by the conventional lithography technique, where the alignment mark region is in clear field, while other regions are in dark field. Next, the nitride layer is patterned by plasma-etching technique to form the nitride alignment mark. The N-well region is formed by lithography and ion-implantation techniques. Thereafter, the P-well region is formed by lithography and ion-implantation methods again. Next, the active device region photoresist is formed by lithography technique. The nitride layer is partially etched to open the windows by plasma-etching technique. The P-well region photoresist is then formed, followed by the deep-implantation process. The second P-well region photoresist is then formed, followed by the deep-implantation process. The field oxide regions for isolation are also grown in the window openings during the P-field drive-in step. Finally, the remaining of nitride layer is removed. This new process can reduce the number of processing steps so as to decrease the production cost.
Inventors
- 👤 Bing-Yau Lu
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 04:01
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0165; H10D84/0191; H10D84/02; H10D84/03; H10D84/038; Y; Y10; Y10S; Y10S148/00; Y10S148/007
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
293 words
A method of fabricating a twin-well integrated circuit device, said method comprising the steps of: (a) forming a pad oxide layer on a P-type semiconductor silicon substrate; (b) forming a nitride layer overlaying said pad oxide layer; (c) forming an alignment mark photoresist pattern overlaying said nitride layer by lithography wherein said alignment mark photoresist pattern is in a clear field, while other regions are in a dark field; (d) partially etching said nitride layer to form a nitride alignment mark pattern by using alignment mark photoresist pattern as a mask; (e) stripping said alignment photoresist pattern; (f) forming a N-well photoresist pattern by lithography; (g) ion-implanting N-type dopants through said pad oxide layer and said nitride layer into said P-type semiconductor substrate to form an N-doped region; (h) removing said N-well photoresist pattern; (i) forming a P-well photoresist pattern by lithography; (j) ion-implanting P-type dopants through said pad oxide layer and said nitride layer into said P-type semiconductor silicon substrate to form a P-doped region; (k) removing said P-well photoresist pattern; (l) first thermally driving in for activating said dopants inside said N-doped and P-doped regions to form N-well and P-well regions; (m) forming an active region photoresist pattern by lithography; (n) partially etching said nitride layer to form an opening window, wherein said opening window is between said N-well and P-well regions; (o) forming the second P-well photoresist pattern by lithography; (p) deep ion-implanting P-type dopants into said P-well regions; (q) removing said second P-well photoresist pattern; (r) second thermally driving in for activating said deep implanted P-type dopants inside said P-well regions, and forming a field oxide region therein said opening window for isolation spontaneously; and (s) removing a remaining part of said pad oxide layer and said nitride layer.
Claim 2
Independent Claim
293 words
A method of fabricating a twin-well integrated circuit device, said method comprising the steps of: (a) forming a pad oxide layer on a P-type semiconductor silicon substrate; (b) forming a nitride layer overlaying said pad oxide layer; (c) forming an alignment mark photoresist pattern overlaying said nitride layer by lithography wherein said alignment mark photoresist pattern is in a clear field, while other regions are in a dark field; (d) partially etching said nitride layer to form a nitride alignment mark pattern by using alignment mark photoresist pattern as a mask; (e) stripping said alignment photoresist pattern; (f) forming a N-well photoresist pattern by lithography; (g) ion-implanting N-type dopants through said pad oxide layer and said nitride layer into said P-type semiconductor substrate to form an N-doped region; (h) removing said N-well photoresist pattern; (i) forming a P-well photoresist pattern by lithography; (j) ion-implanting P-type dopants through said pad oxide layer and said nitride layer into said P-type semiconductor silicon substrate to form a P-doped region; (k) removing said P-well photoresist pattern; (l) first thermally driving in for activating said dopants inside said N-doped and P-doped regions to form N-well and P-well regions; (m) forming an active region photoresist pattern by lithography; (n) partially etching said nitride layer to form an opening window, wherein said opening window is between said N-well and P-well regions; (o) forming the second P-well photoresist pattern by lithography; (p) deep ion-implanting P-type dopants into said P-well regions; (q) removing said second P-well photoresist pattern; (r) second thermally driving in for activating said deep implanted P-type dopants inside said P-well regions, and forming a field oxide region therein said opening window for isolation spontaneously; and (s) removing a remaining part of said pad oxide layer and said nitride layer.
Claim 3
Dependent Claim
35 words
The method of claim 1, wherein said first pad oxide layer which is formed in a temperature of 800° to 1000° C. high-temperature oxygen environment, has a thickness of about between 320 to 380 Angstroms.
Claim 4
Dependent Claim
30 words
The method of claim 1, wherein said first nitride layer which is formed by low pressure chemical vapor deposition (LPCVD) has a thickness of about between 1350 to 1650 Angstroms.
Claim 5
Dependent Claim
45 words
The method of claim 1, wherein said N-doped region which is formed by ion implantation, is doped with Phosphorus (P 31 ) ions, with an implantation energy of 50 to 150 keV, and an implantation dose of 10 11 to 10 13 cm -2 .
Claim 6
Dependent Claim
50 words
The method of claim 1, wherein said P-doped region which is formed by ion implantation, is doped with boron (B 11 ) or borondifluoride (BF 2 ) ions, with an implantation energy of 10 to 80 keV, and an implantation dose of 10 12 to 10 13 cm -2 .
Claim 7
Dependent Claim
23 words
The method of claim 1, wherein said first thermally drive in is performed in the temperature range of 1100° C. to 1200° C.
Claim 8
Dependent Claim
28 words
The method of claim 1, wherein said second thermally drive in is performed in the temperature range of 950° C. to 1050° C. for 200 to 300 minutes.
Claim 9
Dependent Claim
20 words
The method of claim 1, wherein said field oxide region has a thickness of about between 1000 to 2000 Angstroms.
Claim 10
Dependent Claim
16 words
The method of claim 1, wherein said a P-type semiconductor substrate is an N-type semiconductor substrate.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-11-17 | 2001-05-19 | 2001-11-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-11-17 | 2005-05-19 | 2005-11-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-11-17 | 2009-05-19 | 2009-11-18 | $7700.00 | Window Closed / Lapsed |