Method and apparatus for controlling a voltage controlled oscillator tuning range in a frequency synthesizer

Claim 2

A phase lock loop (PLL) for a frequency synthesizer, comprising: a reference oscillator providing a first frequency input signal; a phase detector for comparing the phase of the first frequency input signal to a second frequency input signal and generating an error signal; a loop filter coupled to said phase detector, said loop filter providing a control voltage in response to the error signal; a plurality of voltage controlled oscillator (VCO) circuits receiving the control voltage; a VCO control circuit for individually enabling and disabling each of the plurality of VCO circuits, said plurality of VCO circuits each individually generating an output frequency in response to being-enabled, the VCO control circuit including a delay means for determining the settling time of each individually enabled VCO circuit; a lock detect circuit for determining, based on the control voltage, if the frequency synthesizer has locked on frequency with one of the plurality of VCO circuits, said VCO control circuit ceasing to individually enable and disable each of the plurality of VCO circuits once the frequency synthesizer has locked on frequency; and a loop divider for dividing each generated output frequency by a predetermined amount and feeding a divided frequency back to the phase detector as the second frequency input signal.

Claim 3

A phase lock loop (PLL) for a frequency synthesizer as described in claim 1, wherein the VCO control circuit includes a counter for tracking the number of each individually enabled VCO circuit, said VCO control circuit being disabled once the number reaches a predetermined overflow limit.

Claim 4

A phase lock loop (PLL) for a frequency synthesizer as described in claim 1, wherein the VCO control circuit individually enables and disables each of the plurality of VCO circuits in a non-sequential manner.

Claim 5

A phase lock loop (PLL) for a frequency synthesizer, comprising: a reference oscillator providing a first frequency input signal; a phase detector for comparing the phase of the first frequency input signal to a second frequency input signal and generating an error signal; a loop filter coupled to said phase detector, said loop filter providing a control voltage in response to the error signal; a plurality of voltage controlled oscillator (VCO) circuits receiving the control voltage: a VCO control circuit for individually enabling and disabling each of the plurality of VCO circuits, said plurality of VCO circuits each individually generating an output frequency in response to being enabled; a lock detect circuit for determining, based on the control voltage, if the frequency synthesizer has locked on frequency with one of the plurality of VCO circuits, said VCO control circuit ceasing to individually enable and disable each of the plurality of VCO circuits once the frequency synthesizer has locked on frequency; a loop divider for dividing each generated output frequency by a predetermined amount and feeding a divided frequency back to the phase detector as the second frequency input signal; and wherein the lock detect circuit compares the control voltage to predetermined threshold limits to generate a lock indicator signal, the lock indicator signal indicating either a locked or unlocked synthesizer condition, said VCO control circuit individually enabling and disabling each of the plurality of VCO circuits in response to the lock indicator signal indicating an unlocked condition.

Claim 6

A phase lock loop (PLL) for a frequency synthesizer, comprising: a reference oscillator providing a first frequency input signal; a phase detector for comparing the phase of the first frequency input signal to a second frequency input signal and generating an error signal; a loop filter coupled to said phase detector, said loop filter providing a control voltage in response to the error signal; a plurality of voltage controlled oscillator (VCO) circuits receiving the control voltage: a VCO control circuit for individually enabling and disabling each of the plurality of VCO circuits, said plurality of VCO circuits each individually generating an output frequency in response to being enabled; a lock detect circuit for determining, based on the control voltage, if the frequency synthesizer has locked on frequency with one of the plurality of VCO circuits, said VCO control circuit ceasing to individually enable and disable each of the plurality of VCO circuits once the frequency synthesizer has locked on frequency; a loop divider for dividing each generated output frequency by a predetermined amount and feeding a divided frequency back to the phase detector as the second frequency input signal; and wherein the lock detect circuit compares the control voltage to predetermined threshold limits to generate a lock indicator signal, the lock indicator signal indicating either a locked or unlocked synthesizer condition, said VCO control circuit individually enabling and disabling each of the plurality of VCO circuits in response to the lock indicator signal indicating an unlocked condition.

Claim 7

A phase lock loop (PLL) for a frequency synthesizer, comprising: a reference oscillator providing a first frequency input signal; a phase detector for comparing the phase of the first frequency input signal to a second frequency input signal and generating an error signal; a loop filter coupled to said phase detector, said loop filter providing a control voltage in response to the error signal; a plurality of voltage controlled oscillator (VCO) circuits receiving the control voltage; a lock detect circuit responsive to the control voltage for generating a lock detect signal indicating a locked condition or an unlocked condition of the PLL; a VCO control circuit responsive to the lock detect signal for selectively enabling and disabling each of the plurality of VCO circuits, one at a time, until a locked condition is indicated by the lock detect signal, the VCO control circuit ceasing to selectively enable and disable each of the plurality of VCO circuits when each of the plurality of VCO circuits has been selectively enabled without a locked condition being indicated by the lock detect signal; the plurality of VCO circuits each providing a selectively generated output frequency in response to being enabled; and a loop divider for dividing each selectively generated output frequency by a predetermined amount anal feeding a divided output frequency back to the phase detector as the second frequency input signal.

Claim 8

A phase lock loop (PLL) for a frequency synthesizer, comprising: a reference oscillator providing a first frequency input signal; a phase detector for comparing the phase of the first frequency input signal to a second frequency input signal and generating an error signal; a loop filter coupled to said phase detector, said loop filter providing a control voltage in response to the error signal; a plurality of voltage controlled oscillator (VCO) circuits receiving the control voltage; a lock detect circuit responsive to the control voltage for generating a lock detect signal indicating a locked condition or an unlocked condition of the PLL; a VCO control circuit responsive to the lock detect signal for selectively enabling and disabling each of the plurality of VCO circuits, one at a time, until a locked condition is indicated by the lock detect signal, the VCO control circuit ceasing to selectively enable and disable each of the plurality of VCO circuits when each of the plurality of VCO circuits has been selectively enabled without a locked condition being indicated by the lock detect signal; the plurality of VCO circuits each providing a selectively generated output frequency in response to being enabled; and a loop divider for dividing each selectively generated output frequency by a predetermined amount anal feeding a divided output frequency back to the phase detector as the second frequency input signal.

Claim 9

A phase lock loop (PLL) for a frequency synthesizer as described in claim 5, wherein the plurality of VCO circuits provide partially overlapping frequency ranges.

Claim 10

A voltage controlled oscillator (VCO) tuning circuit for a frequency synthesizer, including: a plurality of VCOs, each providing different and partially overlapping frequency ranges, said plurality of VCOs each generating an output frequency in response to being enabled; a VCO control circuit alternately enabling and disabling each of said plurality of VCOs to provide a tuning range within which the frequency synthesizer can lock on frequency; and wherein the VCO control circuit includes a means for tracking the number of each alternately enabled VCO, said VCO control circuit being disabled in response to the number reaching a predetermined overflow limit.

Claim 11

A voltage controlled oscillator (VCO) tuning circuit for a frequency synthesizer, including: a plurality of VCOs, each providing different and partially overlapping frequency ranges, said plurality of VCOs each generating an output frequency in response to being enabled; a VCO control circuit alternately enabling and disabling each of said plurality of VCOs to provide a tuning range within which the frequency synthesizer can lock on frequency; and wherein the VCO control circuit includes a means for tracking the number of each alternately enabled VCO, said VCO control circuit being disabled in response to the number reaching a predetermined overflow limit.

Claim 12

A VCO tuning circuit for a frequency synthesizer as described in claim 7, wherein the frequency synthesizer locks on frequency with one of the alternately enabled VCOs, and the VCO control circuit ceases alternately enabling and disabling the plurality of VCOs once the frequency synthesizer locks on frequency.

Claim 13

A VCO tuning circuit for a frequency synthesizer as described in claim 7, further including: a lock detect circuit for determining whether the frequency synthesizer has locked on frequency with one of the plurality of VCOs, said lock detect circuit generating a lock indicator signal indicating either a locked or unlocked condition of the frequency synthesizer, said VCO control circuit alternately enabling and disabling each of the plurality of VCOs when an unlocked condition is indicated, and said VCO control circuit terminating the alternate enabling and disabling of the plurality of VCOs when a locked condition is indicated.

Claim 14

A VCO tuning circuit for a frequency synthesizer as described in claim 7, wherein the VCO control circuit includes a delay circuit for maintaining each alternately enabled VCO enabled for a predetermined time.

Claim 19

A method of tuning a PLL in a frequency synthesizer as described in claim 12, wherein the plurality of selectable VCO frequency ranges are partially overlapping.

Claim 20

A phase lock loop (PLL) for a frequency synthesizer, comprising: a reference oscillator providing a first frequency input signal; a phase detector for comparing the phase of the first frequency input signal to a second frequency input signal and generating an error signal; a loop filter coupled to said phase detector, said loop filter providing a control voltage in response to the error signal; a plurality of voltage controlled oscillator (VCO) circuits receiving the control voltage; a VCO control circuit for individually enabling and disabling each of the plurality of VCO circuits, said plurality of VCO circuits each individually generating an output frequency in response to being enabled, the VCO control circuit including a counter for tracking the number of each individually enabled VCO circuit, said VCO control circuit being disabled once the number reaches a predetermined overflow limit; a lock detect circuit for determining, based on the control voltage, if the frequency synthesizer has locked on frequency with one of the plurality of VCO circuits, said VCO control circuit ceasing to individually enable and disable each of the plurality of VCO circuits once the frequency synthesizer has locked on frequency; and a loop divider for dividing each generated output frequency by a predetermined amount and feeding a divided frequency back to the phase detector as the second frequency input signal.

Claim 21

A phase lock loop (PLL) for a frequency synthesizer, comprising: a reference oscillator providing a first frequency input signal; a phase detector for comparing the phase of the first frequency input signal to a second frequency input signal and generating an error signal; a loop filter coupled to said phase detector, said loop filter providing a control voltage in response to the error signal; a plurality of voltage controlled oscillator (VCO) circuits receiving the control voltage; a VCO control circuit for individually enabling and disabling each of the plurality of VCO circuits, said plurality of VCO circuits each individually generating an output frequency in response to being enabled, the VCO control circuit including a counter for tracking the number of each individually enabled VCO circuit, said VCO control circuit being disabled once the number reaches a predetermined overflow limit; a lock detect circuit for determining, based on the control voltage, if the frequency synthesizer has locked on frequency with one of the plurality of VCO circuits, said VCO control circuit ceasing to individually enable and disable each of the plurality of VCO circuits once the frequency synthesizer has locked on frequency; and a loop divider for dividing each generated output frequency by a predetermined amount and feeding a divided frequency back to the phase detector as the second frequency input signal.