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US5686735A Expired / Lapsed US ⏱️ 0.0 years remaining

Silicon-on-insulator (SOI) transistor

Assignee: Samsung Electronics Co Ltd
•
Filing: 1995-02-17
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Granted: 1997-11-11
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Expires: 2015-02-17
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Abstract

Abstract An SOI transistor whose source region and/or drain region have a heterostructure made up of at least two different semiconductor materials, to thereby prevent a bipolar-induced breakdown.

Inventors

  • 👤 Jai-Hoon Sim

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-06 00:57
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/60; H10D30/64; H10D30/66; H10D30/667; H10D30/01; H10D30/021; H10D30/031; H10D30/0321; H10D30/0323; H10D30/67; H10D30/6704; H10D30/6708; H10D30/6713; H10D30/6729; H10D30/673; H10D30/6733; H10D30/6734; H10D30/791; H10D30/797; H10D30/798; H10D86/00; H10D86/201; H10P; H10P90/00; H10P90/19; H10P90/1904; H10P90/1906; H10D30/674; H10D30/6741; H10D30/6743; H10D30/6744

Claims Analysis

Total Claims: 3
Claim 1
Independent Claim 144 words
A silicon-on-insulator (SOI) transistor comprising: a semiconductor substrate; an insulating layer formed on said substrate; a channel region comprised of a single layer of a first semiconductor material formed on said insulating layer, said first semiconductor material being Si; and first and second impurity regions respectively disposed on opposite sides of, and abutting with, said channel region, at least one of said first and second impurity regions being comprised of a heterostructure of at least two layers of second and third semiconductor materials successively formed on said insulating layer, said second and third semiconductor materials being Si and Si 1-x Ge x , respectively and having different energy band gaps, said heterostructure being formed of a first layer of Si, a second layer of Si 1-x Ge x formed on said first layer, and a third layer of Si formed on said second layer.
Claim 2
Dependent Claim 144 words
A silicon-on-insulator (SOI) transistor comprising: a semiconductor substrate; an insulating layer formed on said substrate; a channel region comprised of a single layer of a first semiconductor material formed on said insulating layer, said first semiconductor material being Si; and first and second impurity regions respectively disposed on opposite sides of, and abutting with, said channel region, at least one of said first and second impurity regions being comprised of a heterostructure of at least two layers of second and third semiconductor materials successively formed on said insulating layer, said second and third semiconductor materials being Si and Si 1-x Ge x , respectively and having different energy band gaps, said heterostructure being formed of a first layer of Si, a second layer of Si 1-x Ge x formed on said first layer, and a third layer of Si formed on said second layer.
Claim 3
Dependent Claim 20 words
A SOI transistor according to claim 1, wherein both said first and second impurity regions are comprised of said heterostructure.

References Cited (Backward Citations)

EP0380077A2 Cited
US5475244A Cited
US5166084A Cited
US5420055A Cited
US5461250A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 2000-11-10 2001-05-12 2001-11-11 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2004-11-10 2005-05-12 2005-11-11 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2008-11-10 2009-05-12 2009-11-11 $7700.00 Window Closed / Lapsed

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